On-the-fly Computation Method in Field-Programmable Gate Array for Analog-to-Digital Converter Linearity Testing

This paper presents a new approach to linearity testing of analog-to-digital converters (ADCs) through on-the-fly computation in field-programmable gate array (FPGA) hardware. The proposed method computes the linearity while it is processing without compromising the accuracy of the measurement, so very little overhead time is required to compute the final linearity. The results will be displayed immediately after a single ramp is supplied to the device under test. This is a cost-effective chip testing solution for semiconductor companies, achieved by reducing computing time and utilization of low-cost and low-specification automatic test equipment (ATE). The experimental results showed that the on-the-fly computation method significantly reduced the computation time (up to 44.4%) compared to the conventional process. Thus, for every 100M 12-bit ADC tested with 32 hits per code, the company can save up to 139,972 Php on electricity consumption

On-the-fly computation method in field-programmable gate array for analog-to-digital converter linearity testing

© 2018 Published by ITB Journal Publisher. This paper presents a new approach to linearity testing of analog-to-digital converters (ADCs) through on-the-fly computation in field-programmable gate array (FPGA) hardware. The proposed method computes the linearity while it is processing without compromising the accuracy of the measurement, so very little overhead time is required to compute the final linearity. The results will be displayed immediately after a single ramp is supplied to the device under test. This is a cost-effective chip testing solution for semiconductor companies, achieved by reducing computing time and utilization of low-cost and low-specification automatic test equipment (ATE). The experimental results showed that the on-the-fly computation method significantly reduced the computation time (up to 44.4%) compared to the conventional process. Thus, for every 100M 12-bit ADC tested with 32 hits per code, the company can save up to 139,972 Php on electricity consumption

Built-in self test of RF subsystems

textWith the rapid development of wireless and wireline communications, a variety of new standards and applications are emerging in the marketplace. In order to achieve higher levels of integration, RF circuits are frequently embedded into System on Chip (SoC) or System in Package (SiP) products. These developments, however, lead to new challenges in manufacturing test time and cost. Use of traditional RF test techniques requires expensive high frequency test instruments and long test time, which makes test one of the bottlenecks for reducing IC costs. This research is in the area of built-in self test technique for RF subsystems. In the test approach followed in this research, on-chip detectors are used to calculate circuits specifications, and data converters are used to collect the data for analysis by an on-chip processor. A novel on-chip amplitude detector has been designed and optimized for RF circuit specification test. By using on-chip detectors, both the system performance and specifications of the individual components can be accurately measured. On-chip measurement results need to be collected by Analog to Digital Converters (ADCs). A novel time domain, low power ADC has been designed for this purpose. The ADC architecture is based on a linear voltage controlled delay line. Using this structure results in a linear transfer function for the input dependent delay. The time delay difference is then compared to a reference to generate a digital code. Two prototype test chips were fabricated in commercial CMOS processes. One is for the RF transceiver front end with on-chip detectors; the other is for the test ADC. The 940MHz RF transceiver front-end was implemented with on-chip detectors in a 0.18 [micrometer] CMOS technology. The chips were mounted onto RF Printed Circuit Boards (PCBs), with tunable power supply and biasing knobs. The detector was characterized with measurements which show that the detector keeps linear performance over a wide input amplitude range of 500mV. Preliminary simulation and measurements show accurate transceiver performance prediction under process variations. A 300MS/s 6 bit ADC was designed using the novel time domain architecture in a 0.13 [micrometer] standard digital CMOS process. The simulation results show 36.6dB Signal to Noise Ratio (SNR), 34.1dB Signal to Noise and Distortion Ratio (SNDR) for 99MHz input, Differential Non-Linearity (DNL)<0.2 Least Significant Bit (LSB), and Integral Non-Linearity (INL)<0.5LSB. Overall chip power is 2.7mW with a 1.2V power supply. The built-in detector RF test was extended to a full transceiver RF front end test with a loop-back setup, so that measurements can be made to verify the benefits of the technique. The application of the approach to testing gain, linearity and noise figure was investigated. New detector types are also evaluated. In addition, the low-power delay-line based ADC was characterized and improved to facilitate gathering of data from the detector. Several improved ADC structures at the system level are also analyzed. The built-in detector based RF test technique enables the cost-efficient test for SoCs.Electrical and Computer Engineerin

High-speed Time-interleaved Digital-to-Analog Converter (TI-DAC) for Self-Interference Cancellation Applications

Nowadays, the need for higher data-rate is constantly growing to enhance the quality of the daily communication services. The full-duplex (FD) communication is exemplary method doubling the data-rate compared to half-duplex one. However, part of the strong output signal of the transmitter interferes to the receiver-side because they share the same antenna with limited attenuation and, as a result, the receiver’s performance is corrupted. Hence, it is critical to remove the leakage signal from the receiver’s path by designing another block called self-interference cancellation (SIC). The main goal of this dissertation is to develop the SIC block embedded in the current-mode FD receivers. To this end, the regenerated cancellation current signal is fed to the inputs of the base-band filter and after the mixer of a (direct-conversion) current-mode FD receiver. Since the pattern of the transmitter (the digital signal generated by DSP) is known, a high-speed digital-to-Analog converter (DAC) with medium-resolution can perfectly suppress main part of the leakage on the receiver path. A capacitive DAC (CDAC) is chosen among the available solutions because it is compatible with advanced CMOS technology for high-speed application and the medium-resolution designs. Although the main application of the design is to perform the cancellation, it can also be employed as a stand-alone DAC in the Analog (I/Q) transmitter. The SIC circuitry includes a trans-impedance amplifier (TIA), two DACs, high-speed digital circuits, and built-in-self-test section (BIST). According to the available specification for full-duplex communication system, the resolution and working frequency of the CDAC are calculated (designed) equal to 10-bit (3 binary+ 2 binary + 5 thermometric) and 1GHz, respectively. In order to relax the design of the TIA (settling time of the DAC), the CDAC implements using 2-way time-interleaved (TI) manner (the effective SIC frequency equals 2GHz) without using any calibration technique. The CDAC is also developed with the split-capacitor technique to lower the negative effects of the conventional binary-weighted DAC. By adding one extra capacitor on the left-side of the split-capacitor, LSB-side, the value of the split-capacitor can be chosen as an integer value of the unit capacitor. As a result, it largely enhances the linearity of the CADC and cancellation performance. If the block works as a stand-alone DAC with non-TI mode, the digital input code representing a Sinus waveform with an amplitude 1dB less than full-scale and output frequency around 10.74MHz, chosen by coherent sampling rule, then the ENOB, SINAD, SFDR, and output signal are 9.4-bit, 58.2 dB, 68.4dBc, and -9dBV. The simulated value of the |DNL| (static linearity) is also less than 0.7. The similar simulation was done in the SIC mode while the capacitive-array woks in the TI mode and cancellation current is set to the full-scale. Hence, the amount of cancelling the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. equals 51.3dB, 15.1 dB, 24dBc, 66.4 dB. The designed SIC cannot work as a closed-loop design. The layout was optimally drawn in order to minimize non-linearity, the power-consumption of the decoders, and reduce the complexity of the DAC. By distributing the thermometric cells across the array and using symmetrical switching scheme, the DAC is less subjected to the linear and gradient effect of the oxide. Based on the post-layout simulation results, the deviation of the design after drawing the layout is studied. To compare the results of the schematic and post-layout designs, the exact conditions of simulation above (schematic simulations) are used. When the block works as a stand-alone CDAC, the ENOB, SINAD, SFDR are 8.5-bit, 52.6 dB, 61.3 dBc. The simulated value of the |DNL| (static linearity) is also limited to 1.3. Likewise, the SI signal at the output of the TIA, SNDR, SFDR, SNDRequ. are equal to 44dB, 11.7 dB, 19 dBc, 55.7 dB

Alternative Methods for Non-Linearity Estimation in High-Resolution Analog-to-Digital Converters

The evaluation of the linearity performance of a high resolution Analog-to- Digital Converter (ADC) by the Standard Histogram method is an outstanding challenge due to the requirement of high purity of the input signal and the high number of output data that must be acquired to obtain an acceptable accuracy on the estimation. These requirements become major application drawbacks when the measures have to be performed multiple times within long test flows and for many parts, and under an industrial environment that seeks to reduce costs and lead times as is the case in the New Space sector. This thesis introduces two alternative methods that succeed in relaxing the two previous requirements for the estimation of the Integral Nonlinearity (INL) parameter in ADCs. The methods have been evaluated by estimating the Integral Non-Linearity pattern by simulation using realistic high-resolution ADC models and experimentally by applying them to real high performance ADCs. First, the challenge of applying the Standard Histogram method for the evaluation of static parameters in high resolution ADCs and how the drawbacks are accentuated in the New Space industry is analysed, being a highly expensive method for an industrial environment where cost and lead time reduction is demanded. Several alternative methods to the Standard Histogram for estimating Integral Nonlinearity in high resolution ADCs are reviewed and studied. As the number of existing works in the literature is very large and addressing all of them is a challenge in itself, only those most relevant to the development of this thesis have been included. Methods based on spectral processing to reduce the number of data acquired for the linearity test and methods based on a double histogram to be able to use generators that do not meet the the purity requirement against the ADC to be tested are further analysed. Two novel contributions are presented in this work for the estimation of the Integral Nonlinearity in ADCs, as possible alternatives to the Standard Histogram method. The first method, referred to as SSA (Simple Spectral Approach), seeks to reduce the number of output data that need to be acquired and focuses on INL estimation using an algorithm based on processing the spectrum of the output signal when a sinusoidal input stimulus is used. This type of approach requires a much smaller number of samples than the Standard Histogram method, although the estimation accuracy will depend on how smooth or abrupt the ADC nonlinearity pattern is. In general, this algorithm cannot be used to perform a calibration of the ADC nonlinearity error, but it can be applied to find out between which limits it lies and what its approximate shape is. The second method, named SDH (Simplified Double Histogram)aims to estimate the Non-Linearity of the ADC using a poor linearity generator. The approach uses two histograms constructed from the two set of output data in response to two identical input signals except for a dc offset between them. Using a simple adder model, an extended approach named ESDH (Extended Simplified Double Histogram) addresses and corrects for possible time drifts during the two data acquisitions, so that it can be successfully applied in a non-stationary test environment. According to the experimental results obtained, the proposed algorithm achieves high estimation accuracy. Both contributions have been successfully tested in high-resolution ADCs with both simulated and real laboratory experiments, the latter using a commercial ADC with 14-bit resolution and 65Msps sampling rate (AD6644 from Analog Devices).La medida de la característica de linealidad de un convertidor analógicodigital (ADC) de alta resolución mediante el método estándar del Histograma constituye un gran desafío debido los requisitos de alta pureza de la señal de entrada y del elevado número de datos de salida que deben adquirirse para obtener una precisión aceptable en la estimación. Estos requisitos encuentran importantes inconvenientes para su aplicación cuando las medidas deben realizarse dentro de largos flujos de pruebas, múltiples veces y en un gran número de piezas, y todo bajo un entorno industrial que busca reducir costes y plazos de entrega como es el caso del sector del Nuevo Espacio. Esta tesis introduce dos métodos alternativos que consiguen relajar los dos requisitos anteriores para la estimación de los parámetros de no linealidad en los ADCs. Los métodos se han evaluado estimando el patrón de No Linealidad Integral (INL) mediante simulación utilizando modelos realistas de ADC de alta resolución y experimentalmente aplicándolos en ADCs reales. Inicialmente se analiza el reto que supone la aplicación del método estándar del Histograma para la evaluación de los parámetros estáticos en ADCs de alta resolución y cómo sus inconvenientes se acentúan en la industria del Nuevo Espacio, siendo un método altamente costoso para un entorno industrial donde se exige la reducción de costes y plazos de entrega. Se estudian métodos alternativos al Histograma estándar para la estimación de la No Linealidad Integral en ADCs de alta resolución. Como el número de trabajos es muy amplio y abordarlos todos es ya en sí un desafío, se han incluido aquellos más relevantes para el desarrollo de esta tesis. Se analizan especialmente los métodos basados en el procesamiento espectral para reducir el número de datos que necesitan ser adquiridos y los métodos basados en un doble histograma para poder utilizar generadores que no cumplen el requisito de precisión frente al ADC a medir. En este trabajo se presentan dos novedosas aportaciones para la estimación de la No Linealidad Integral en ADCs, como posibles alternativas al método estándar del Histograma. El primer método, denominado SSA (Simple Spectral Approach), busca reducir el número de datos de salida que es necesario adquirir y se centra en la estimación de la INL mediante un algoritmo basado en el procesamiento del espectro de la señal de salida cuando se utiliza un estímulo de entrada sinusoidal. Este tipo de enfoque requiere un número mucho menor de muestras que el método estándar del Histograma, aunque la precisión de la estimación dependerá de lo suave o abrupto que sea el patrón de no-linealidad del ADC a medir. En general, este algoritmo no puede utilizarse para realizar una calibración del error de no linealidad del ADC, pero puede aplicarse para averiguar entre qué límites se encuentra y cuál es su forma aproximada. El segundo método, denominado SDH (Simplified Double Histogram) tiene como objetivo estimar la no linealidad del ADC utilizando un generador de baja pureza. El algoritmo utiliza dos histogramas, construidos a partir de dos conjuntos de datos de salida en respuesta a dos señales de entrada idénticas, excepto por un desplazamiento constante entre ellas. Utilizando un modelo simple de sumador, un enfoque ampliado denominado ESDH (Extended Simplified Double Histogram) aborda y corrige las posibles derivas temporales durante las dos adquisiciones de datos, de modo que puede aplicarse con éxito en un entorno de prueba no estacionario. De acuerdo con los resultados experimentales obtenidos, el algoritmo propuesto alcanza una alta precisión de estimación. Ambas contribuciones han sido probadas en ADCs de alta resolución con experimentos tanto simulados como reales en laboratorio, estos últimos utilizando un ADC comercial con una resolución de 14 bits y una tasa de muestreo de 65Msps (AD6644 de Analog Devices)

Energy-efficient analog-to-digital conversion for ultra-wideband radio

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 207-222).In energy constrained signal processing and communication systems, a focus on the analog or digital circuits in isolation cannot achieve the minimum power consumption. Furthermore, in advanced technologies with significant variation, yield is traditionally achieved only through conservative design and a sacrifice of energy efficiency. In this thesis, these limitations are addressed with both a comprehensive mixed-signal design methodology and new circuits and architectures, as presented in the context of an analog-to-digital converter (ADC) for ultra-wideband (UWB) radio. UWB is an emerging technology capable of high-data-rate wireless communication and precise locationing, and it requires high-speed (>500MS/s), low-resolution ADCs. The successive approximation register (SAR) topology exhibits significantly reduced complexity compared to the traditional flash architecture. Three time-interleaved SAR ADCs have been implemented. At the mixed-signal optimum energy point, parallelism and reduced voltage supplies provide more than 3x energy savings. Custom control logic, a new capacitive DAC, and a hierarchical sampling network enable the high-speed operation. Finally, only a small amount of redundancy, with negligible power penalty, dramatically improves the yield of the highly parallel ADC in deep sub-micron CMOS.by Brian P. Ginsburg.Ph.D