3,002 research outputs found

    Dynamic Assembly for System Adaptability, Dependability, and Assurance

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    (DASASA) ProjectAuthor-contributed print ite

    RESTful Wireless Sensor Networks

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    Sensor networks have diverse structures and generally employ proprietary protocols to gather useful information about the physical world. This diversity generates problems to interact with these sensors since custom APIs are needed which are tedious, error prone and have steep learning curve. In this thesis, I present RESThing, a lightweight REST framework for wireless sensor networks to ease the process of interacting with these sensors by making them accessible over the Web. I evaluate the system and show that it is feasible to support widely used and standard Web protocols in wireless sensor networks. Being able to integrate these tiny devices seamlessly into the global information medium, we can achieve the Web of Things

    Automated RTL generator

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    Code generation is a vast topic and has been discussed and implemented for quite a while now. It has been also been a topic of debate as to what is an ideal code generator and how an ideal code generator can be created. The biggest challenge while creating a code generator is to maintain a balance between the amount of freedom given to the user and the restrictions imposed on the code generated. These two seemed to be very conflicting requirements while designing the Automated RTL Code Generator. If the code generator tries to be rigid and sticks to well-defined paths and restricted code, the flexibility provided to the also reduces. It is a very interesting task to strike the right amount of balance and generate code of high quality and well-defined standards. Verilog code is a type of RTL (Register Transfer Level) that itself has fewer constructs and variety as compared to pure software languages like Java, or Python so it makes sense to generate it automatically so that the hardware designers are relieved from the mundane tasks of writing repetitive verilog code modules. Also code generator provides a nice introduction to the much wider topic of compiler design. This project also tries to delve deeper into the latest IPXACT XML standard IEEE 1865-2009 which is used for hardware description and will provide means of generating verilog code directly from it

    Mapping Large Scale Research Metadata to Linked Data: A Performance Comparison of HBase, CSV and XML

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    OpenAIRE, the Open Access Infrastructure for Research in Europe, comprises a database of all EC FP7 and H2020 funded research projects, including metadata of their results (publications and datasets). These data are stored in an HBase NoSQL database, post-processed, and exposed as HTML for human consumption, and as XML through a web service interface. As an intermediate format to facilitate statistical computations, CSV is generated internally. To interlink the OpenAIRE data with related data on the Web, we aim at exporting them as Linked Open Data (LOD). The LOD export is required to integrate into the overall data processing workflow, where derived data are regenerated from the base data every day. We thus faced the challenge of identifying the best-performing conversion approach.We evaluated the performances of creating LOD by a MapReduce job on top of HBase, by mapping the intermediate CSV files, and by mapping the XML output.Comment: Accepted in 0th Metadata and Semantics Research Conferenc
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