Crosstalk-free Conjugate Networks for Optical Multicast Switching

High-speed photonic switching networks can switch optical signals at the rate of several terabits per second. However, they suffer from an intrinsic crosstalk problem when two optical signals cross at the same switch element. To avoid crosstalk, active connections must be node-disjoint in the switching network. In this paper, we propose a sequence of decomposition and merge operations, called conjugate transformation, performed on each switch element to tackle this problem. The network resulting from this transformation is called conjugate network. By using the numbering-schemes of networks, we prove that if the route assignments in the original network are link-disjoint, their corresponding ones in the conjugate network would be node-disjoint. Thus, traditional nonblocking switching networks can be transformed into crosstalk-free optical switches in a routine manner. Furthermore, we show that crosstalk-free multicast switches can also be obtained from existing nonblocking multicast switches via the same conjugate transformation.Comment: 10 page

A new scheme to realize crosstalk-free permutations in optical MINs with vertical stacking

©2002 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.Vertical stacking is an alternative for constructing nonblocking multistage interconnection networks (MINs). In this paper, we study the crosstalk-free permutation in rearrangeable, self-routing Banyan-type optical MINs built on vertical stacking and propose a new scheme for realizing permutations in this class of optical MINs crosstalk-free. The basic idea of the new scheme is to classify permutations into permutation classes such that all permutations in one class share the same crosstalk-free decomposition pattern. By running the Euler-Split based crosstalk-free decomposition only once for a permutation class and applying the obtained crosstalk-free decomposition pattern to all permutations in the class, crosstalk-free decomposition of permutations can be realized in a more efficient way. We show that the number of permutations in a permutation class is huge, enabling the average time complexity of the new scheme to realize a crosstalk-free permutation in an N by N network to be reduced to O(N) from previously O(NlogN).Xiaohong Jiang, Hong Shen, Md. Mamun-ur-Rashid Khandker, Susumu Horiguch

Parallel routing and wavelength assignment for optical multistage interconnection networks

Multistage interconnection networks (MINs) are among the most efficient switching architectures in terms of the number of switching elements (SEs) used. For op-tical MINs (OMINs), two I/O connections with neigh-boring wavelengths cannot share a common SE due to crosstalk. In this paper, we focus on the wavelength di-lation approach, in which the I/O connections shar-ing a common SE will be assigned different wavelengths with enough wavelength spacing. We first study the per-mutation capacity of OMINs, then propose fast par-allel routing and wavelength assignment algorithms for OMINs. By applying our permutation decomposi-tion and graph coloring techniques, the proposed algo-rithms can route any permutation without crosstalk in wavelength-rearrangeable space-strict-sense Banyan net-works and wavelength-rearrangeable space-rearrangeable Benes networks in polylogarithmic time using a linear num-ber of processors. 1

Symmetric rearrangeable networks and algorithms

A class of symmetric rearrangeable nonblocking networks has been considered in this thesis. A particular focus of this thesis is on Benes networks built with 2 x 2 switching elements. Symmetric rearrangeable networks built with larger switching elements have also being considered. New applications of these networks are found in the areas of System on Chip (SoC) and Network on Chip (NoC). Deterministic routing algorithms used in NoC applications suffer low scalability and slow execution time. On the other hand, faster algorithms are blocking and thus limit throughput. This will be an acceptable trade-off for many applications where achieving ”wire speed” on the on-chip network would require extensive optimisation of the attached devices. In this thesis I designed an algorithm that has much lower blocking probabilities than other suboptimal algorithms but a much faster execution time than deterministic routing algorithms. The suboptimal method uses the looping algorithm in its outermost stages and then in the two distinct subnetworks deeper in the switch uses a fast but suboptimal path search method to find available paths. The worst case time complexity of this new routing method is O(NlogN) using a single processor, which matches the best known results reported in the literature. Disruption of the ongoing communications in this class of networks during rearrangements is an open issue. In this thesis I explored a modification of the topology of these networks which gives rise to what is termed as repackable networks. A repackable topology allows rearrangements of paths without intermittently losing connectivity by breaking the existing communication paths momentarily. The repackable network structure proposed in this thesis is efficient in its use of hardware when compared to other proposals in the literature. As most of the deterministic algorithms designed for Benes networks implement a permutation of all inputs to find the routing tags for the requested inputoutput pairs, I proposed a new algorithm that can work for partial permutations. If the network load is defined as ρ, the mean number of active inputs in a partial permutation is, m = ρN, where N is the network size. This new method is based on mapping the network stages into a set of sub-matrices and then determines the routing tags for each pair of requests by populating the cells of the sub-matrices without creating a blocking state. Overall the serial time complexity of this method is O(NlogN) and O(mlogN) where all N inputs are active and with m < N active inputs respectively. With minor modification to the serial algorithm this method can be made to work in the parallel domain. The time complexity of this routing algorithm in a parallel machine with N completely connected processors is O(log^2 N). With m active requests the time complexity goes down to (logmlogN), which is better than the O(log^2 m + logN), reported in the literature for 2^0.5((log^2 -4logN)^0.5-logN)<= ρ <= 1. I also designed multistage symmetric rearrangeable networks using larger switching elements and implement a new routing algorithm for these classes of networks. The network topology and routing algorithms presented in this thesis should allow large scale networks of modest cost, with low setup times and moderate blocking rates, to be constructed. Such switching networks will be required to meet the bandwidth requirements of future communication networks

Blocking performance of extended pruned vertically stacked optical banyan structure under different link failure conditions

The blocking performance of extended pruned vertically stacked optical banyan (VSOB) networks under different link failure conditions has been analyzed in this paper. We applied plane fixed routing with linear search and plane fixed routing with random search algorithms to route the optical data through the network in our simulation. Our simulation results show that adding one or two extra planes to the pruned VSOB network reduces the blocking probability significantly. Beyond two extra planes, the decrease of blocking probability is not so significant. A close approximation of the minimum number of planes required to make the extended pruned vertically stacked optical banyan networks nonblocking has been presented