Automatic Tuning of Digital Circuits.

Variation in transistors is increasing as process technology transistor dimensions shrink. Compounded with lowering supply voltage, this increased variation presents new challenges for the circuit designer. However, this variation also brings many new opportunities for the circuit designer to leverage as well. We present a time-to-digital converter embedded inside a 64-bit processor core, for direct monitoring of on-chip critical paths. This path monitoring allows the processor to monitor process variation and run-time variations. By adjusting to both static and dynamic operating conditions the impact of variations can be reduced. The time-to-digital converter achieves high-resolution measurement in the picosecond range, due to self-calibration via a self-feedback mode. This system is implemented in 45nm silicon and measured silicon results are shown. We also examine techniques for enhanced variation-tolerance in subthreshold digital circuits, applying these to a high fan-in, self-timed transition detection circuit that, due to its self-timing, is able to fully compensate for the large variation in subthreshold. In addition to mitigating variations we also leverage them for random number generation. We demonstrate that the randomness inherent in the oxide breakdown process can be extracted and applied for the specific applications of on-chip ID generation and on-chip true random number generation. By using dynamic automated self-calibrating algorithms that tune and control the on-chip circuitry, we are able to achieve extremely high-quality results. The two systems are implemented in 65 nm silicon. Measured results for the on-chip ID system, called OxID, show a high-degree of randomness and read-stability in the generated IDs, both primary prerequisites of a high-quality on-chip ID system. Measured results for the true random number generator, called OxiGen, show an exceptionally high degree of randomness, passing all fifteen NIST 800-22 tests for randomness with statistical significance and without the aid of a post-processor.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/86390/1/rachliu_1.pd

A MEMS BASED MICROWAVE PIXEL FOR UWB RADAR BASED 3-D DIAGNOSTIC IMAGING

A MEMS-based microwave Pixel has been developed for use with an Ultra-wideband (UWB) radar probe for high-resolution 3-D non-contact, non-ionizing tomographic diagnostic imaging of the thorax. In the proposed system, an UWB radar transmits a 400 ps duration pulse in the frequency range of 3.1 GHz to 5.1 GHz. The transmitted pulse penetrates through the tissues and is partially reflected at each tissue interface characterized by a complex permittivity change. A suitable microwave lens focuses the reflected wavefront on a 2-D array of MEMS-based microwave Pixels to illuminate each Pixel to a tiny 2-D section of the reflected wavefront. Each Pixel with a footprint area of 595 x 595 μm2 is designed to have 144 parallel connected microfabricated inductors, each with an inductance of 12.439 nH, and a single 150 μm×150 μm microfabricated deformable diaphragm based variable capacitor to generate a voltage which is the dielectric signature of the respective tissue section. A 2-D array of such Pixels can be used to generate a voltage map that corresponds to the dielectric property distribution of the target area. The high dielectric contrast between the healthy and diseased tissues, enable a high precision diagnostics of medical conditions in a non-invasive non-contact manner. This thesis presents the analytical design, 3-D finite element simulation results, and a fabrication process to realize the proposed microwave imaging Pixel. The proposed Pixel with total inductance of 86.329 pH and capacitance tuning range of 1.68:1, achieved a sensitivity of 4.5 aF/0.8 μA.m-1 to generate tomographic coronal imaging slices of human thorax deep upto 4.2 cm enabling a theoritical lateral resolution of 0.59 mm

Stabilised Control of Converter Interfaced DERs for Reliable Operation of Microgrid and Microgrid Clusters

This thesis aims to achieve a stabilised control of converter interfaced DER for the reliable and resilient operation of microgrid and microgrid clusters. The suitability of voltage and current control for VSCs is evaluated and corrective measures are proposed to stabilise converter operation. Furthermore, the accurate power demand distribution in islanded MGs and interconnected MGs are ensured by advanced control strategies. The proposal presented in the thesis is verified both through simulation and experimental work

Performance of direct power controlled grid-connected voltage source converters

PhD ThesisIn this thesis the performance of direct power controlled grid-connected voltage source converters (VSCs) is investigated. Of particular interest is the stability of the controller with the third-order LCL filter employed as the grid filter, effect of grid impedance variations and grid voltage distortion, and current limitation during voltage dips. The control scheme implemented is virtual-flux direct power control with space vector modulation (VF-DPC-SVM). By mathematical modelling and stability analysis, it is found that the closed-loop power control system is stable for all values of proportional gain when the current sensors are on the inverter side of the LCL filter. The inverter current together with the estimated grid virtual-flux is used to estimate the active power and the reactive power. The difference between the estimated reactive power and the reactive power on the grid side is compensated for, using a new reactive power error compensation scheme based on the estimated capacitor current. The control system is found to be robust to changes in grid inductance, and remains stable for a range of grid inductance values, and controller proportional gain. It is demonstrated in simulation and experimentally that the total harmonic distortion (THD) of the current injected by the VSC is less than the limit of 5 %, set by standards, for all different values of grid inductance and proportional gain. This is true even in the presence of significant grid voltage distortion. To control the VSC during voltage dips without damaging the semiconductor devices, a new current limiting algorithm is proposed and implemented. The positive-sequence component of the virtual-flux is used for synchronization and power estimation to achieve balanced, undistorted currents during unsymmetrical voltage dips. Experimental results show that the current achieved during unsymmetrical voltage dips is balanced and has a THD of less than 3 %.Commonwealth Scholarship and Fellowship Plan, Copperbelt Universit

Research study on multi-KW-DC distribution system

A detailed definition of the HVDC test facility and the equipment required to implement the test program are provided. The basic elements of the test facility are illustrated, and consist of: the power source, conventional and digital supervision and control equipment, power distribution harness and simulated loads. The regulated dc power supplies provide steady-state power up to 36 KW at 120 VDC. Power for simulated line faults will be obtained from two banks of 90 ampere-hour lead-acid batteries. The relative merits of conventional and multiplexed power control will be demonstrated by the Supervision and Monitor Unit (SMU) and the Automatically Controlled Electrical Systems (ACES) hardware. The distribution harness is supported by a metal duct which is bonded to all component structures and functions as the system ground plane. The load banks contain passive resistance and reactance loads, solid state power controllers and active pulse width modulated loads. The HVDC test facility is designed to simulate a power distribution system for large aerospace vehicles