Use of Field Programmable Gate Array Technology in Future Space Avionics

Fulfilling NASA's new vision for space exploration requires the development of sustainable, flexible and fault tolerant spacecraft control systems. The traditional development paradigm consists of the purchase or fabrication of hardware boards with fixed processor and/or Digital Signal Processing (DSP) components interconnected via a standardized bus system. This is followed by the purchase and/or development of software. This paradigm has several disadvantages for the development of systems to support NASA's new vision. Building a system to be fault tolerant increases the complexity and decreases the performance of included software. Standard bus design and conventional implementation produces natural bottlenecks. Configuring hardware components in systems containing common processors and DSPs is difficult initially and expensive or impossible to change later. The existence of Hardware Description Languages (HDLs), the recent increase in performance, density and radiation tolerance of Field Programmable Gate Arrays (FPGAs), and Intellectual Property (IP) Cores provides the technology for reprogrammable Systems on a Chip (SOC). This technology supports a paradigm better suited for NASA's vision. Hardware and software production are melded for more effective development; they can both evolve together over time. Designers incorporating this technology into future avionics can benefit from its flexibility. Systems can be designed with improved fault isolation and tolerance using hardware instead of software. Also, these designs can be protected from obsolescence problems where maintenance is compromised via component and vendor availability.To investigate the flexibility of this technology, the core of the Central Processing Unit and Input/Output Processor of the Space Shuttle AP101S Computer were prototyped in Verilog HDL and synthesized into an Altera Stratix FPGA

Active Polymeric Materials for 3D Shaping and Sensing

Part I: Reprogrammable Chemical 3D Shaping for Origami, Kirigami, and Reconfigurable Molding Origami- and kirigami-based design principles have recently received strong interest from the scientific and engineering communities because they offer fresh approaches to engineering of structural hierarchy and adaptive functions in materials, which could lead to many promising applications. Herein, we present a reprogrammable 3D chemical shaping strategy for creating a wide variety of stable complex origami and kirigami structures autonomously. This strategy relies on a reverse patterning method that encodes prescribed 3D geometric information as a spatial pattern of the unlocked phase (dispersed phase) in the locked phase (matrix phase) in a pre-stretched Nafion sheet. Building upon the unique chemical reprogramming capability of the Nafion shape memory polymer, we have developed a reconfigurable molding technology that can significantly reduce the time, cost, and waste in 3D shaping of various materials with high fidelity. Part II: A Versatile, Multifunctional, Polymer-Based Dynamically Responsive Interference Coloration The bioinspired stimuli-responsive structural coloration offers a wide variety of potential applications, ranging from sensing to camouflage to intelligent textiles. Owing to its design simplicity, which does not require multilayers of materials with alternative refractive indices or micro- and nanostructures, thin film interference represents a promising solution towards scalable and affordable manufacturing of high-quality responsive structural coloration systems. However, thin films of polymers with appropriate thickness generally do not exhibit visible structural colors if they are directly deposited on substrates with relatively low refractive indices such as glass and polydimethylsiloxane (PDMS). Here, a versatile technology that enables polymer-based, stimuli-responsive interference coloration (RIC) on various substrates is presented. Real-time, continuous, colorimetric RIC sensors for humidity, organic vapor, temperature, and mechanical force are demonstrated by using different stimuli-responsive polymers. The transparent RIC film on glass shows strong coupling of constructive interference reflected colors and complementary destructive interference transmitted colors on opposite sides of the film. The ability to use substrates such as glass and PDMS allows for the proof-of-concept demonstration of a humidity-sensing window, and a self-reporting, self-acting sensor that does not consume external power

Embedded processors on FPGA: Hard-core vs Soft-core

Field Programmable Gate Arrays (FPGAs) are integrated circuits (ICs) that can be reprogrammed by the consumer after manufacturing. They are based on a matrix of configurable logic blocks connected via programmable interconnects that enables the designer to quickly recreate hardware circuits. In the past, FPGAs were primarily used for prototyping and debugging purposes. However, with their increased popularity, many commercial products now incorporate FPGAs. In the late 1990s, FPGA vendors introduced System-on-chip (SoC) devices that housed one or more hard-core processors and an FPGA fabric on a single IC to allow for more complex designs that involved hardware and software co-integration. While this approach provides advantages of running your design at much higher speeds it does not provide the flexibility of modification to suit the application. Because of this many FPGA vendors provide the solution of using soft-core processors that are configured from logic resources inside the FPGA. While this approach provides the advantage of flexibility they run at about 30% to 50% of the speed of the hard-core processors. Thus each approach has its own advantages and disadvantages. In this thesis, an application was developed to run on two different FPGA platforms. The first platform, Digilent Zybo FPGA board, houses an ARM-Cortex hard-core while the other, Digilent Nexys-4 board, implemented ARM-Cortex soft-core using FPGA resources. IP blocks were designed in Hardware Description Languages Verilog and VHDL to interface with the processor and it’s supported Bus Architecture (AXI/AHB). The application was written in C and assembly language and enacted the function of a Digital Oscilloscope. It used the ADC ports on the FPGA board to continuously read analog signals and plotted them as a dynamic waveform on a VGA monitor. Xilinx Vivado was the primary IDE used for HDL design, synthesis, simulation and implementation for both the platforms. Reports generated from Vivado as well as the run-time results were used to compare the two platforms and identify their strengths and weaknesses. Also discussed is the methodology for choosing either board over the other

FPGA design methodology for industrial control systems—a review

This paper reviews the state of the art of fieldprogrammable gate array (FPGA) design methodologies with a focus on industrial control system applications. This paper starts with an overview of FPGA technology development, followed by a presentation of design methodologies, development tools and relevant CAD environments, including the use of portable hardware description languages and system level programming/design tools. They enable a holistic functional approach with the major advantage of setting up a unique modeling and evaluation environment for complete industrial electronics systems. Three main design rules are then presented. These are algorithm refinement, modularity, and systematic search for the best compromise between the control performance and the architectural constraints. An overview of contributions and limits of FPGAs is also given, followed by a short survey of FPGA-based intelligent controllers for modern industrial systems. Finally, two complete and timely case studies are presented to illustrate the benefits of an FPGA implementation when using the proposed system modeling and design methodology. These consist of the direct torque control for induction motor drives and the control of a diesel-driven synchronous stand-alone generator with the help of fuzzy logic

Monolithic Integration Piezoelectric Resonators on CMOS for Radio-Frequency and Sensing Applications

Software cognitive radios and Internet of Things (IoT) are recent interest areas that need low loss and low power consumption hardware. More specifically, the area of software cognitive radios requires that hardware be frequency agile and highly selective. Meanwhile, IoT relies on multiple low power sensor networks. By combining Complementary Metal Oxide Semiconductors (CMOS) technology with piezoelectric Micro-Electro-Mechanical Systems (MEMS), we can fabricate Systems-on-Chip (SoC) that can be used as filters or references (oscillators) and highly selective sensors. In this work we developed a die-level compatible process for the monolithic integration of Bulk Acoustic Resonators (BAWs) on CMOS for low power, reduced area and high-quality passives for radio frequency applications. Using CMOS as a fabrication substrate some stringent requirements were added to maintain the dies and the technology’s integrity. A few of these limitations were the need for a low thermal budget fabrication process, die handling and electro-static discharge (ESD) protection. The devices were first fabricated on glass for modeling extraction that was later used for the design of the integrated circuits (IC). Three integrated circuits were designed as substrates for the integration using IBM’s 180nm and TSMC’s 65nm technology. A monolithic BAW oscillator with a resonance frequency of 1.8GHz was demonstrated with an FOM ~186dBc/Hz, comparable to other academia work. Using the developed process, a membrane BAW structure (FBAR) was integrated as well. Using a susceptor coating and zinc oxide’s (ZnO) high temperature coefficient of frequency (TCF) the device was studied as an alternative uncooled infrared sensor. Finally, a reprogrammable IC and an RF PCB were designed for volatile organic compound (VOC) testing using self-assembled monolayers (SAMs) as the absorber layer

Underwater acoustic modem with streaming video capabilities

Oceans have shown tremendous importance and impact on our lives. Thus the need for monitoring and protecting the oceans has grown exponentially in recent years. On the other hand, oceans have economical and industrial potential in areas such as pharmaceutical, oil, minerals and biodiversity. This demand is increasing and the need for high data rate and near real-time communications between submerged agents became of paramount importance. Among the needs for underwater communications, streaming video (e.g. for inspecting risers or hydrothermal vents) can be seen as the top challenge, which when solved will make all the other applications possible. Presently, the only reliable approach for underwater video streaming relies on wired connections or tethers (e.g. from ROVs to the surface) which presents severe operational constraints that makes acoustic links together with AUVs and sensor networks strongly appealing. Using new polymer-based acoustic transducers, which in very recent works have shown to have bandwidth and power efficiency much higher than the usual ceramics, this article proposes the development of a reprogrammable acoustic modem for operating in underwater communications with video streaming capabilities. The results have shown a maximum data-rate of 1Mbps with a simple modulation scheme such as OOK, at a distance of 20 m.FCT (Fundacao para a Ciencia e Tecnologia) in the scope of the project: PEst-OE/EEA/UI04436/2015; Project Scope: PEst-UID/CECI00319/201

Programmable logic devices: a test approach for the Input / Output blocks and Pad-to-Pin interconnections

Dynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have their functionality partially modified at run-time without stopping the operation of the whole system. The efficient management of the logic space available is one of the biggest problems faced by these systems. When the sequence of reconfigurations to be performed is not predictable, resource allocation decisions have to be made on-line. A rearrangement may be necessary to get enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance.A new software tool that helps to handle the problems posed by the consecutive reconfiguration of the same logic space is presented in this paper. This tool uses a novel on-line rearrangement procedure to solve fragmentation problems and to rearrange the logic space in a way completely transparent to the applications currently running