Field Programmable Port Extender (FPX) User Guide (Version 2.2)

This manual summarizes how to insert the Field Programmable Port Extender (FPX) into the Washington University Gigabit Switch (WUGS), how to install the NCHARGE control software, how to initialize the system, and how to reprogram a user-defined module into the FPX over the network using the included web-based tools

10 Gigabit-capable Passive Optical Network Transmission Convergence layer design

Uusien laajakaistaisten tietoliikennepalvelujen ja kasvavan tiedonsiirtokapasiteetin tarpeen myötä kiinteiden liityntäverkkojen infrastruktuuri on muuttumassa sähköisestä optiseksi. Euroopan komission rahoittamassa Scalable Advanced Ring-based passive Dense Access Network Architecture (SARDANA)-tutkimusprojektissa tutkitaan seuraavan sukupolven passiivisten optisten liityntäverkojen teknologioita. Projektin päätavoitteena on pienentää passiivisiin optisiin liityntäverkkoihin liittyviä kustannuksia. Tämä diplomityö käsittelee SARDANA-testiverkon standardoimattoman 10 Gigabit-capable Passive Optical Network (XGPON) Transmission Convergence (TC)-kerroksen suunnittelua ja ensimmäistä toteutusta optisessa verkkopäätteessä (ONU:ssa). TC-kerros toteuttaa Medium Access Control (MAC)-protokollan. SARDANA XGPON TC (SXGTC)-kerros perustuu standardoituun ITU-T G.984.3 Gigabit-capable Passive Optical Network (GPON) TC (GTC)-kerroksen [ITU08] tarjoamaan ratkaisuun mutta eroaa tästä yksityiskohdiltaan. Kaikki SXGTC-kerroksen oleelliset yksityiskohdat peilataan GTC-kerrokseen. Suunniteltu SXGTC-protokolla tukee maksimissaan 9.95328 Gbps:n symmetrisiä tiedonsiirtonopeuksia. SXGTC-protokolla on optimoitu käsittelemään dataa 8 tavun sanoissa. Ensimmäinen ONU SXGTC-kerroksen toteutus ohjelmoitavassa Field Programmable Gate Array (FPGA)-piirissä esitellään funktionaalisten lohkojen avulla. Tämän implementaation tiedonsiirtonopeus alasuunnassa on 9.95328 Gbps 98 %:n kaistatehokkuudella ja yläsuunnassa 2.48832 Gbps 94.5 %:n kaistatehokkuudella SARDANA-testiverkkokonfiguraation tapauksessa.With the emergence of new broadband telecommunication services and constantly increasing bandwidth demand, fixed access network infrastructure is evolving from electrical to optical. The European Commission funded research project Scalable Advanced Ring-based passive Dense Access Network Architecture (SARDANA) researches the next-generation passive optical access network technologies. The main goal of the project is to reduce expenses that are related to passive optical access networks. This master's thesis discusses the design of the non-standardized 10 Gigabit-capable Passive Optical Network (XGPON) Transmission Convergence (TC) layer and its first implementation version for Optical Network Unit (ONU) for the SARDANA test network. The SARDANA XGPON TC (SXGTC) layer implements the Medium Access Control (MAC) protocol. The SXGTC layer is based on the standardized solution offered by the ITU-T G.984.3 Gigabit-capable Passive Optical Network (GPON) TC (GTC) layer recommendation [ITU08] but differs from it in many details. All the SXGTC layer features are compared to those of the GTC layer. As a result, the SXGTC protocol is able to support operation on up to 9.95328 Gbps symmetrical transmission rates. The SXGTC layer is optimized for the 8-byte-word-based data processing. The first ONU SXGTC layer Field Programmable Gate Array (FPGA) implementation is presented in terms of functional blocks. The implementation supports operation on 9.95328 Gbps in the downstream offering 98 % bandwidth efficiency and on 2.48832 Gbps in the upstream offering 94.5 % bandwidth efficiency for the SARDANA test network configuration

The Open Network Laboratory (a resource for high performance networking research)

The Open Network Laboratory (ONL) is a remotely accessible network testbed designed to enable network researchers to conduct experiments using high performance routers and applications. ONL™s Remote Laboratory Interface (RLI) allows users to easily configure a network topology, initialize and modify the routers™ routing tables, packet classification tables and queuing parameters. It also enables users to add software plugins to the embedded processors available at each of the routers™ ports, enabling the introduction of new functionality. The routers provide a large number of built-in counters to track various aspects of system usage, and the RLI software makes these available through easy-to-use real-time charts. This allows researchers to expose what is happening fiunder the surfacefl enabling them to develop the insights needed to understand system behavior in complex situations and to deliver compelling demonstrations of their ideas in a realistic operating environment. This paper provides an overview of ONL, emphasizing how it can be used to carry out a wide range of networking experiments

FPgrep and FPsed: Packet Payload Processors for Managing the Flow of Digital Content on Local Area Networks and the Internet

As computer networks increase in speed, it becomes difficult to monitor and manage the transmitted digital content. To alleviate these problems, hardware-based search (FPgrep) and search-and-replace (FPsed) modules have been developed. FP-grep has the ability to scan packet payloads for a given set of regular expressions and pass or drop packets based on the payload contents. FPsed also scans packet payloads for a set of regular expressions and adds the ability to modify the payload if desired. The hardware circuits that implement the FPgrep and FPsed modules can be generated, compiled, and synthesized using a simple web interface. Once a module is created it is programmed into logic on a Field Programmable Gate Array (FPGA). The FPgrep and FPsed modules use FPGAs to process packets at the full rate of Gigabit-speed networks. Both modules, along with several supporting applications were developed and tested using the Field Programmable Port Extender (FPX) platform. Applications developed for the modules currently include a spam filter, virus protection, an information security filter, as well as a copyright enforcement function

HAIL: An Algorithm for the Hardware Accelerated Identification of Languages, Master\u27s Thesis, May 2006

This thesis examines in detail the Hardware-Accelerated Identification of Languages (HAIL) project. The goal of HAIL is to provide an accurate means to identify the language and encoding used in streaming content, such as documents passed over a high-speed network. HAIL has been implemented on the Field-programmable Port eXtender (FPX), an open hardware platform developed at Washington University in St. Louis. HAIL can accurately identify the primary languages and encodings used in text at rates much higher than what can be achieved by software algorithms running on microprocessors

An architecture and technology for Ambient Intelligence Node

The era of separate networks is over. The existing technology leaders are preparing a big change in recreation of environment around us. There are several faces for this change. Names like Ambient Intelligence, Ambient Network, IP Multimedia Subsystem and others were created all over the Globe. Regardless of which name is used the new network will combine three main functional principles---it will be: contextual aware, ubiquitous access and intelligent interfaces unified network. Within this thesis two major aspects are defined. First, the definition of the Ambient Intelligence Environment concept is presented. Secondly the architecture vectors for the technology are named. A short overview of the existing technology is followed by details for the chosen technology---FPGA. The overall specifications are incorporated in the design and demonstration of a basic Ambient Intelligence Node created in the System on the Chip (SoC) FPGA technology

FPGA-based architectures for next generation communications networks

This engineering doctorate concerns the application of Field Programmable Gate Array (FPGA) technology to some of the challenges faced in the design of next generation communications networks. The growth and convergence of such networks has fuelled demand for higher bandwidth systems, and a requirement to support a diverse range of payloads across the network span. The research which follows focuses on the development of FPGA-based architectures for two important paradigms in contemporary networking - Forward Error Correction and Packet Classification. The work seeks to combine analysis of the underlying algorithms and mathematical techniques which drive these applications, with an informed approach to the design of efficient FPGA-based circuits

System architecture and hardware implementations for a reconfigurable MPLS router

With extremely wide bandwidth and good channel properties, optical fibers have brought fast and reliable data transmission to today’s data communications. However, to handle heavy traffic flowing through optical physical links, much faster processing speed is required or else congestion can take place at network nodes. Also, to provide people with voice, data and all categories of multimedia services, distinguishing between different data flows is a requirement. To address these router performance, Quality of Service /Class of Service and traffic engineering issues, Multi-Protocol Label Switching (MPLS) was proposed for IP-based Internetworks. In addition, routers flexible in hardware architecture in order to support ever-evolving protocols and services without causing big infrastructure modification or replacement are also desirable. Therefore, reconfigurable hardware implementation of MPLS was proposed in this project to obtain the overall fast processing speed at network nodes. The long-term goal of this project is to develop a reconfigurable MPLS router, which uniquely integrates the best features of operations being conducted in software and in run-time-reconfigurable hardware. The scope of this thesis includes system architecture and service algorithm considerations, Verilog coding and testing for an actual device. The hardware and software co-design technique was used to partition and schedule the protocol code for execution on both a general-purpose processor and stream-based hardware. A novel RPS scheme that is practically easy to build and can realize pipelined packet-by-packet data transfer at each output was proposed to take the place of the traditional crossbar switching. In RPS, packets with variable lengths can be switched intelligently without performing packet segmentation and reassembly. Primary theoretical analysis of queuing issues was discussed and an improved multiple queue service scheduling policy UD-WRR was proposed, which can reduce packet-waiting time without sacrificing the performance. In order to have the tests carried out appropriately, dedicated circuitry for the MPLS functional block to interface a specific MAC chip was implemented as well. The hardware designs for all functions were realized with a single Field Programmable Gate Array (FPGA) device in this project. The main result presented in this thesis was the MPLS function implementation realizing a major part of layer three routing at the reconfigurable hardware level, which advanced a great step towards the goal of building a router that is both fast and flexible

Using embedded hardware monitor cores in critical computer systems

The integration of FPGA devices in many different architectures and services makes monitoring and real time detection of errors an important concern in FPGA system design. A monitor is a tool, or a set of tools, that facilitate analytic measurements in observing a given system. The goal of these observations is usually the performance analysis and optimisation, or the surveillance of the system. However, System-on-Chip (SoC) based designs leave few points to attach external tools such as logic analysers. Thus, an embedded error detection core that allows observation of critical system nodes (such as processor cores and buses) should enforce the operation of the FPGA-based system, in order to prevent system failures. The core should not interfere with system performance and must ensure timely detection of errors. This thesis is an investigation onto how a robust hardware-monitoring module can be efficiently integrated in a target PCI board (with FPGA-based application processing features) which is part of a critical computing system. [Continues.