4 research outputs found

    Adaptive Receiver Design for High Speed Optical Communication

    Get PDF
    Conventional input/output (IO) links consume power, independent of changes in the bandwidth demand by the system they are deployed in. As the system is designed to satisfy the peak bandwidth demand, most of the time the IO links are idle but still consuming power. In big data centers, the overall utilization ratio of IO links is less than 10%, corresponding to a large amount of energy wasted for idle operation. This work demonstrates a 60 Gb/s high sensitivity non-return-to-zero (NRZ) optical receiver in 14 nm FinFET technology with less than 7 ns power-on time. The power on time includes the data detection, analog bias settling, photo-diode DC current cancellation, and phase locking by the clock and data recovery circuit (CDR). The receiver autonomously detects the data demand on the link via a proposed link protocol and does not require any external enable or disable signals. The proposed link protocol is designed to minimize the off-state power consumption and power-on time of the link. In order to achieve high data-rate and high-sensitivity while maintaining the power budget, a 1-tap decision feedback equalization method is applied in digital domain. The sensitivity is measured to be -8 dBm, -11 dBm, and -13 dBm OMA (optical modulation amplitude) at 60 Gb/s, 48 Gb/s, and 32 Gb/s data rates, respectively. The energy efficiency in always-on mode is around 2.2 pJ/bit for all data-rates with the help of supply and bias scaling. The receiver incorporates a phase interpolator based clock-and-data recovery circuit with approximately 80 MHz jitter-tolerance corner frequency, thanks to the low-latency full custom CDR logic design. This work demonstrates the fastest ever reported CMOS optical receiver and runs almost at twice the data-rate of the state-of-the-art CMOS optical receiver by the time of the publication. The data-rate is comparable to BiCMOS optical receivers but at a fraction of the power consumption

    Broadband Receiver Electronic Circuits for Fiber-Optical Communication Systems

    Get PDF
    The exponential growth of internet traffic drives datacenters to constantly improve their capacity. As the copper based network infrastructure is being replaced by fiber-optical interconnects, new industrial standards for higher datarates are required. Several research and industrial organizations are aiming towards 400 Gb Ethernet and beyond, which brings new challenges to the field of high-speed broadband electronic circuit design. Replacing OOK with higher M-ary modulation formats and using higher datarates increases network capacity but at the cost of power. With datacenters rapidly becoming significant energy consumers on the global scale, the energy efficiency of the optical interconnect transceivers takes a primary role in the development of novel systems. There are several additional challenges unique in the design of a broadband shortreach fiber-optical receiver system. The sensitivity of the receiver depends on the noise performance of the PD and the electronics. The overall system noise must be optimized for the specific application, modulation scheme, PD and VCSEL characteristics. The topology of the transimpedance amplifier affects the noise and frequency response of the PD, so the system must be optimized as a whole. Most state-of-the-art receivers are built on high-end semiconductor SiGe and InP technologies. However, there are still several design decisions to be made in order to get low noise, high energy efficiency and adequate bandwidth. In order to overcome the frequency limitations of the optoelectronic components, bandwidth enhancement and channel equalization techniques are used. In this work several different blocks of a receiver system are designed and characterized. A broadband, 50 GHz bandwidth CB-based TIA and a tunable gain equalizer are designed in a 130 nm SiGe BiCMOS process. An ultra-broadband traveling wave amplifier is presented, based on a 250 nm InP DHBT technology demonstrating a 207 GHz bandwidth. Two TIA front-end topologies with 133 GHz bandwidth, a CB and a CE with shunt-shunt feedback, based on a 130 nm InP DHBT technology are designed and compared

    Wideband integrated circuits for optical communication systems

    Get PDF
    The exponential growth of internet traffic drives datacenters to constantly improvetheir capacity. Several research and industrial organizations are aiming towardsTbps Ethernet and beyond, which brings new challenges to the field of high-speedbroadband electronic circuit design. With datacenters rapidly becoming significantenergy consumers on the global scale, the energy efficiency of the optical interconnecttransceivers takes a primary role in the development of novel systems. Furthermore,wideband optical links are finding application inside very high throughput satellite(V/HTS) payloads used in the ever-expanding cloud of telecommunication satellites,enabled by the maturity of the existing fiber based optical links and the hightechnology readiness level of radiation hardened integrated circuit processes. Thereare several additional challenges unique in the design of a wideband optical system.The overall system noise must be optimized for the specific application, modulationscheme, PD and laser characteristics. Most state-of-the-art wideband circuits are builton high-end semiconductor SiGe and InP technologies. However, each technologydemands specific design decisions to be made in order to get low noise, high energyefficiency and adequate bandwidth. In order to overcome the frequency limitationsof the optoelectronic components, bandwidth enhancement and channel equalizationtechniques are used. In this work various blocks of optical communication systems aredesigned attempting to tackle some of the aforementioned challenges. Two TIA front-end topologies with 133 GHz bandwidth, a CB and a CE with shunt-shunt feedback,are designed and measured, utilizing a state-of-the-art 130 nm InP DHBT technology.A modular equalizer block built in 130 nm SiGe HBT technology is presented. Threeultra-wideband traveling wave amplifiers, a 4-cell, a single cell and a matrix single-stage, are designed in a 250 nm InP DHBT process to test the limits of distributedamplification. A differential VCSEL driver circuit is designed and integrated in a4x 28 Gbps transceiver system for intra-satellite optical communications based in arad-hard 130nm SiGe process
    corecore