109 research outputs found
A Reconfigurable Outer Modem Platform for Future Communications Systems
Future mobile and wireless communications networks
require flexible modem architectures with high performance.
Efficient utilization of
application specific flexibility is key to fulfill these
requirements.
For high throughput a single processor can not provide
the necessary computational power.
Hence multi-processor architectures become necessary.
This paper presents a multi-processor platform based on a new
dynamically reconfigurable application specific instruction set processor (dr-ASIP)
for the application domain of channel decoding.
Inherently parallel decoding tasks can be mapped onto individual processing nodes.
The implied challenging inter-processor communication is efficiently handled
by a Network-on-Chip (NoC) such that the throughput of each node is not degraded.
The dr-ASIP features Viterbi and Log-MAP decoding
for support of convolutional and turbo codes
of more than 10 currently specified mobile and wireless standards.
Furthermore, its flexibility allows for adaptation to future systems
Reconfigurable Turbo/Viterbi Channel Decoder in the Coarse-Grained Montium Architecture
Mobile wireless communication systems become multi-mode systems. These future mobile systems employ multiple wireless communication standards, which are different by means of algorithms that are used to implement the baseband processing and the channel decoding. Efficient implementation of multiple wireless standards in mobile terminals requires energy-efficient and flexible hardware. We propose to implement both the baseband processing and channel decoding in a heterogeneous reconfigurable system-on-chip. The system-on-chip contains many processing elements of different granularities, which includes our coarse-grained reconfigurable MONTIUM architecture. We already showed the feasibility to implement the baseband processing of OFDM and WCDMA based communication systems in the MONTIUM. In this paper we implemented two kinds of channel decoders in the same MONTIUM architecture: Viterbi and Turbo decoding
Flexible Multi-ASIP SoC for Turbo/LDPC Decoder
International audienceIn order to meet flexibility and performance constraints of current and future digital communication applications, multiple ASIPs combined with dedicated communication and memory architectures are required. In this work we consider the design of an innovative universal channel decoder architecture model by unifying flexibility-oriented and optimization-oriented approaches. Towards this objective, we have designed a flexible and scalable multiprocessor platform based on a novel ASIP architecture for high throughput turbo/LDPC decoding. The proposed platform supports turbo and LDPC codes of most emerging wireless communication standards (WiFi, WiMax, LTE, and DVB-RCS). Energy-aware optimisation techniques have been also proposed and implemented. Finally, a fully functional FPGA demonstrator is available and the proposed Multi-ASIP architecture has been successfully integrated into a new generation telecom chip
State of the art baseband DSP platforms for Software Defined Radio: A survey
Software Defined Radio (SDR) is an innovative approach which is becoming a more and more promising technology for future mobile handsets. Several proposals in the field of embedded systems have been introduced by different universities and industries to support SDR applications. This article presents an overview of current platforms and analyzes the related architectural choices, the current issues in SDR, as well as potential future trends.Peer reviewe
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