Variable Fractional Digital Delay Filter on Reconfigurable Hardware

This thesis describes a design for a variable fractional delay (VFD) finite impulse reponse (FIR) filter implemented on reconfigurable hardware. Fractionally delayed signals are required for several audio-based applications, including echo cancellation and musical signal analysis. Traditionally, VFD FIR filters have been implemented using a fixed structure in software based upon the order of the filter. This fixed structure restricts the range of valid fractional delay values permitted by the filter. This proposed design implements an order-scalable FIR filter, permitting fractionally delayed signals of widely varying integer sizes. Furthermore, the proposed design of this thesis builds upon the traditional Lagrange interpolator FIR filter using either asoftware-based coefficient computational unit or hardware-based coefficient computational unit in reconfigurable hardware for updating the FIR coefficients in real-time. Traditional Lagrange interpolator FIR filters have only permitted fixed fractional delay. However, by leveraging todays (2012) low-cost high performance reconfigurable hardware, an FIR-based fractional delay filter was created to permit varying fractional delay. A software/hardware hybrid VFD filter was prototyped using the Xilinx System Generator toolkit. The resulting real-time VFD FIR filter was tested usingSystem Generator, as well as Xilinx ISE and ModelSim.M.S., Computer Engineering -- Drexel University, 201

Mapping DSP algorithms to a reconfigurable architecture Adaptive Wireless Networking (AWGN)

This report will discuss the Adaptive Wireless Networking project. The vision of the Adaptive Wireless Networking project will be given. The strategy of the project will be the implementation of multiple communication systems in dynamically reconfigurable heterogeneous hardware. An overview of a wireless LAN communication system, namely HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in a dynamically reconfigurable architecture are discussed. Suggestions for future activities in the Adaptive Wireless Networking project are also given

A Reconfigurable Tile-Based Architecture to Compute FFT and FIR Functions in the Context of Software-Defined Radio

Software-defined radio (SDR) is the term used for flexible radio systems that can deal with multiple standards. For an efficient implementation, such systems require appropriate reconfigurable architectures. This paper targets the efficient implementation of the most computationally intensive kernels of two significantly different standards, viz. Bluetooth and HiperLAN/2, on the same reconfigurable hardware. These kernels are FIR filtering and FFT. The designed architecture is based on a two-dimensional arrangement of 17 tiles. Each tile contains a multiplier, an adder, local memory and multiplexers allowing flexible communication with the neighboring tiles. The tile-base data path is complemented with a global controller and various memories. The design has been implemented in SystemC and simulated extensively to prove equivalence with a reference all-software design. It has also been synthesized and turns out to outperform significantly other reconfigurable designs with respect to speed and area

Design exploration and performance strategies towards power-efficient FPGA-based achitectures for sound source localization

Many applications rely on MEMS microphone arrays for locating sound sources prior to their execution. Those applications not only are executed under real-time constraints but also are often embedded on low-power devices. These environments become challenging when increasing the number of microphones or requiring dynamic responses. Field-Programmable Gate Arrays (FPGAs) are usually chosen due to their flexibility and computational power. This work intends to guide the design of reconfigurable acoustic beamforming architectures, which are not only able to accurately determine the sound Direction-Of-Arrival (DoA) but also capable to satisfy the most demanding applications in terms of power efficiency. Design considerations of the required operations performing the sound location are discussed and analysed in order to facilitate the elaboration of reconfigurable acoustic beamforming architectures. Performance strategies are proposed and evaluated based on the characteristics of the presented architecture. This power-efficient architecture is compared to a different architecture prioritizing performance in order to reveal the unavoidable design trade-offs

Memory-efficient and fast run-time reconfiguration of regularly structured designs

Previous work has shown that run-time reconfiguration of FPGAs benefits greatly from the use of Tunable LUT (TLUT) circuits. These can be rapidly transformed into a specialized LUT circuit and are also very memory efficient when representing regularly structured designs, where the same hardware module is instantiated many times. However, the memory requirements and reconfiguration time of a run-time reconfigurable application are also dependent on the reconfiguration mechanism. In this paper, we will show that the memory requirements of conventional ICAP reconfiguration grow very fast with the number of modules, resulting in excessive memory usage. We propose to use Shift-Register-LUT (SRL) reconfiguration which is faster and results in a memory usage that is independent of the number of modules

Design and analysis of a control system for an optical delay-line circuit used as reconfigurable gain equalizer

The design and analysis of a control system for a coherent two-port lattice-form optical delay-line circuit used as reconfigurable gain equalizer is presented. The design of the control system, which is based on a real device model and a least-square optimization method, is described in detail. Analysis on a five-stage device for the 32 possible solutions of phase parameters showed that, for some filter characteristics, the variations in power dissipation can vary up to a factor of 2. Furthermore, the solution selection has influence on the optimization result and number of iterations needed. A sensitivity analysis of the phase parameters showed that the allowable error in the phase parameters should not exceed a standard deviation of /spl pi//500 in order to achieve a total maximal absolute accuracy error not greater than approximately 0.6 dB. A five-stage device has been fabricated using planar lightwave circuit technology that uses the thermooptic effect. Excellent agreement between simulations and measurements has been achieved

Multi-standard programmable baseband modulator for next generation wireless communication

Considerable research has taken place in recent times in the area of parameterization of software defined radio (SDR) architecture. Parameterization decreases the size of the software to be downloaded and also limits the hardware reconfiguration time. The present paper is based on the design and development of a programmable baseband modulator that perform the QPSK modulation schemes and as well as its other three commonly used variants to satisfy the requirement of several established 2G and 3G wireless communication standards. The proposed design has been shown to be capable of operating at a maximum data rate of 77 Mbps on Xilinx Virtex 2-Pro University field programmable gate array (FPGA) board. The pulse shaping root raised cosine (RRC) filter has been implemented using distributed arithmetic (DA) technique in the present work in order to reduce the computational complexity, and to achieve appropriate power reduction and enhanced throughput. The designed multiplier-less programmable 32-tap FIR-based RRC filter has been found to withstand a peak inter-symbol interference (ISI) distortion of -41 dB