Mapping DSP algorithms to a reconfigurable architecture Adaptive Wireless Networking (AWGN)

This report will discuss the Adaptive Wireless Networking project. The vision of the Adaptive Wireless Networking project will be given. The strategy of the project will be the implementation of multiple communication systems in dynamically reconfigurable heterogeneous hardware. An overview of a wireless LAN communication system, namely HiperLAN/2, and a Bluetooth communication system will be given. Possible implementations of these systems in a dynamically reconfigurable architecture are discussed. Suggestions for future activities in the Adaptive Wireless Networking project are also given

The Chameleon Architecture for Streaming DSP Applications

We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool

Non-power-of-Two FFTs: Exploring the Flexibility of the Montium TP

Coarse-grain reconfigurable architectures, like the Montium TP, have proven to be a very successful approach for low-power and high-performance computation of regular digital signal processing algorithms. This paper presents the implementation of a class of non-power-of-two FFTs to discover the limitations and Flexibility of the Montium TP for less regular algorithms. A non-power-of-two FFT is less regular compared to a traditional power-of-two FFT. The results of the implementation show the processing time, accuracy, energy consumption and Flexibility of the implementation

Design of an efficient binary phase-shift keying based IEEE 802.15.4 transceiver architecture and its performance analysis

The IEEE 802.15.4 physical layer (PHY) standard is one of the communication standards with wireless features by providing low-power and low-data rates in wireless personal area network (WPAN) applications. In this paper, an efficient IEEE 802.15.4 digital transceiver hardware architecture is designed using the binary phase-shift keying (BPSK) technique. The transceiver mainly has transmitter and receiver modules along with the error calculation unit. The BPSK modulation and demodulation are designed using a digital frequency synthesizer (DFS). The DFS is used to generate the in-phase (I) and quadrature-phase (Q) signals and also provides better system performance than the conventional voltage-controlled oscillator (VCO) and look up table (LUT) based memory methods. The differential encoding-decoding mechanism is incorporated to recover the bits effectively and to reduce the hardware complexity. The simulation results are illustrated and used to find the error bits. The design utilizes less chip area, works at 268.2 MHz, and consumes 108 mW of total power. The IEEE 802.15.4 transceiver provides a latency of 3.5 clock cycles and works with a throughput of 76.62 Mbps. The bit error rate (BER) of 2×10-5 is achieved by the proposed digital transceiver and is suitable for real-time applications. The work is compared with existing similar approaches with better improvement in performance parameters

Synchronization in wireless communications

The last decade has witnessed an immense increase of wireless communications services in order to keep pace with the ever increasing demand for higher data rates combined with higher mobility. To satisfy this demand for higher data rates, the throughput over the existing transmission media had to be increased. Several techniques were proposed to boost up the data rate: multicarrier systems to combat selective fading, ultra wide band (UWB) communications systems to share the spectrum with other users, MIMO transmissions to increase the capacity of wireless links, iteratively decodable codes (e.g., turbo codes and LDPC codes) to improve the quality of the link, cognitive radios, and so forth

Doctor of Philosophy

dissertationPortable electronic devices will be limited to available energy of existing battery chemistries for the foreseeable future. However, system-on-chips (SoCs) used in these devices are under a demand to offer more functionality and increased battery life. A difficult problem in SoC design is providing energy-efficient communication between its components while maintaining the required performance. This dissertation introduces a novel energy-efficient network-on-chip (NoC) communication architecture. A NoC is used within complex SoCs due it its superior performance, energy usage, modularity, and scalability over traditional bus and point-to-point methods of connecting SoC components. This is the first academic research that combines asynchronous NoC circuits, a focus on energy-efficient design, and a software framework to customize a NoC for a particular SoC. Its key contribution is demonstrating that a simple, asynchronous NoC concept is a good match for low-power devices, and is a fruitful area for additional investigation. The proposed NoC is energy-efficient in several ways: simple switch and arbitration logic, low port radix, latch-based router buffering, a topology with the minimum number of 3-port routers, and the asynchronous advantages of zero dynamic power consumption while idle and the lack of a clock tree. The tool framework developed for this work uses novel methods to optimize the topology and router oorplan based on simulated annealing and force-directed movement. It studies link pipelining techniques that yield improved throughput in an energy-efficient manner. A simulator is automatically generated for each customized NoC, and its traffic generators use a self-similar message distribution, as opposed to Poisson, to better match application behavior. Compared to a conventional synchronous NoC, this design is superior by achieving comparable message latency with half the energy

Plataforma para projeto de sistemas de rádio definidos por software

Mestrado em Engenharia Electrónica e TelecomunicaçõesEste trabalho tem como objetivos o projeto e a realização de uma plataforma para desenvolvimento de sistemas baseados em tecnologia Software Defined Radio (SDR). Num sistema SDR todas as tarefas de um rádio (ou pelo menos banda base e eventualmente Frequência Intermédia), anteriormente efetuadas por hardware especifico num contexto analógico, são efetuadas no domínio digital por software ou hardware reconfigurável. Esta característica confere a este tipo de rádio uma maior simplicidade, em termos de hardware bem como maior flexibilidade, pois o mesmo dispositivo pode executar diferentes funções apenas alterando o seu firmware/software. Existem diferentes abordagens relativas ao uso desta tecnologia, quer ao nível da arquitetura usada (varia consoante a frequência onde ocorre a digitalização do sinal), quer relativas á topologia de utilização (controlada por hardware reconfigurável, rotinas de software ou ambos). A motivação deste trabalho resulta na necessidade de concepção de uma plataforma para fins académicos baseada num hardware reprogramável, Field Programmable Gate Array (FPGA), de baixo custo, flexível, com interfaces de comunicação digitais e analógicas e que faculte a possibilidade de ser usada em diferentes topologias de utilização. Efetuada a especificação e o estudo necessário ao projeto bem como a escolha apropriada de componentes, conseguiu-se uma plataforma baseada num módulo FPGA contendo um dispositivo Xilinx, da família Spartan-6, bem como outro hardware relevante. A comunicação com outros dispositivos é assegurada por interfaces USB e gigabit Ethernet. A plataforma concebida está também equipada com interfaces analógicas (conversores AD/DA) bem como algumas interfaces de integração com o utilizador consistindo em switches e LEDs. Em suma foi projetada e desenhada uma plataforma aberta e flexível, que pode ser usada com todas as ferramentas de desenvolvimento, programação e depuração, com fácil acesso a todos os sinais relevantes potenciando a sua utilização para efeitos de ensino e investigação em SDR.The main objective of this dissertation relies on projecting and designing a platform suitable for Software De ned Radio (SDR) system development. On an SDR system all, or at least base band and maybe Intermediate Frequency (IF) radio functions, before handled by analog speci c hardware, are now performed on the digital domain by software or an recon gurable hardware device. This feature provides to this type of radios a major simplicity regarding hardware as well as another exibility level since, through a rmware/software upgrade, the same equipment can perform di erent functions. There are some approaches related to the used of this technology, either regarding architecture implementation (they di er in which frequency the digitalization occurs) or utilization topologies (an SDR device can be controlled by a recon gurable hardware, software routines or both). This project's motivation results from the need of designing a exible, low-cost platform, to be used on academic purposes, in which the central component would be a recon gurable hardware, a Field Programmable Gate Array (FPGA). It must provide both analog and digital interfaces so that can be used on various utilization scenarios. Accomplished all the necessary study, design and hardware selection the result is a platform based on an FPGA module, containing an Xilinx device from the Spartan-6 family as well as other relevant hardware. The interaction with other devices is ensured by both gigabit Ethernet and 2.0 Universal Serial Bus (USB) connections. The platform also features analog interfaces (AD/DA converters) as well as some digital end-user interfaces performed by switches and Light Emiter Diodes (LED)s. Concluding, it was built an open and exible platform in which can be use with all provided development, programming and debugging tools and all the relevant signals have easy access enhancing its use for teaching and researching on SDR technology