Low-Complexity Reconfigurable DCT-V Architecture

This brief presents a low-complexity, reconfigurable architecture for the Discrete Cosine Transform (DCT) of type V (DCT-V) of length 32. The proposed architecture can be reconfigured to compute five DCT-V of length 4 with negligible area overhead. As the DCT-V is one of the odd type transforms employed in the Adaptive Multiple Transform (AMT) scheme, the effect of fixed point implementation has been assessed in the Joint Exploration Model (JEM) developed by the JVET group for the Versatile-Video-Coding (VVC) forthcoming standard. Simulation results show that the proposed architecture is not only low-complexity and reconfigurable, but features also imperceptible quality loss. Moreover, when implemented in 90 nm CMOS technology it occupies only 90k eq. gates running at 187 MHz

Design and Implementation of Image Compression Encoder using Orthogonal Approximation DCT

Image Compression is usually carried out using discrete cosine transform (DCT) because compressed image using DCT will take less memory to store the image and quality of the image will be good compared JPEG and HEVC. But, in this work an attempt is made to achieve compression using Approximation DCT (ADCT). ADCT is useful for reducing its computational complexity without affecting its coding performance. It provides better image and video compression compared to the DCT. ADCT is orthogonal and it has lower structural complexity compared to DCT. The unique feature of the ADCT is that it could be configured for the computation of the 32 point ADCT or for parallel computation of two16 point ADCTs or four 8 points ADCTs. It has many advantages in terms of orthogonality, structural simplicity and lower computational complexity. The proposed ADCT is implemented using Verilog and Simulated by ModelSim and synthesized by Xilinx ISE 9.1i. Results are compared with 16 point ADCT with 16 point DCT implementation. The target device is XC5vtx330t-2ff1738. The 16 point ADCT implementation results in a saving of 28.37% IOBs and 63% of LUTs, compared to existing 16 point DCT implementation

A High performance and low cost hardware arcitecture for H.264 transform and quantization algorithms

In this paper, we present a high performance and low cost hardware architecture for real-time implementation of forward transform and quantization and inverse transform and quantization algorithms used in H.264 / MPEG4 Part 10 video coding standard. The hard-ware architecture is based on a reconfigurable datapath with only one multiplier. This hardware is designed to be used as part of a complete low power H.264 video coding system for portable appli-cations. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 81 MHz in a Xilinx Virtex II FPGA and it is verified to work at 210 MHz in a 0.18´ ASIC implementation. The FPGA and ASIC implementations can code 27 and 70 VGA frames (640x480) per second respectively

Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core

This paper describes the mapping of a two-dimensional inverse discrete cosine transform (2-D IDCT) onto a wordlevel reconfigurable Montium Processor. This shows that the IDCT is mapped onto the Montium tile processor (TP) with reasonable effort and presents performance numbers in terms of energy consumption, speed and silicon costs. The Montium results are compared with the IDCT implementation on three other architectures: TI DSP, ASIC and ARM

High Level Design of adaptive distributed controller for Partial Dynamic reconfiguration in FPGA

International audienceControlling dynamic and partial reconfigurations becomes one of the most important key issues in modern embedded systems design. In fact, in such systems, the reconfiguration controller can significantly affect the system performances. Indeed, the controller has to handle efficiently three major tasks during runtime: observation (monitoring), taking reconfiguration decisions and notify decisions to the rest of the system in order to realize it. We present in this paper a novel high level approach permitting to model, using MARTE UML profile, modular and flexible distributed controllers for dynamic reconfiguration management. This approach permits components/ models reuse and allows systematic code generation. It consequently makes reconfigurable systems design less tedious and reduces time to market