Crosstalk-free Conjugate Networks for Optical Multicast Switching

High-speed photonic switching networks can switch optical signals at the rate of several terabits per second. However, they suffer from an intrinsic crosstalk problem when two optical signals cross at the same switch element. To avoid crosstalk, active connections must be node-disjoint in the switching network. In this paper, we propose a sequence of decomposition and merge operations, called conjugate transformation, performed on each switch element to tackle this problem. The network resulting from this transformation is called conjugate network. By using the numbering-schemes of networks, we prove that if the route assignments in the original network are link-disjoint, their corresponding ones in the conjugate network would be node-disjoint. Thus, traditional nonblocking switching networks can be transformed into crosstalk-free optical switches in a routine manner. Furthermore, we show that crosstalk-free multicast switches can also be obtained from existing nonblocking multicast switches via the same conjugate transformation.Comment: 10 page

Blocking Probability of f -Cast Optical Banyan Networks on Vertical Stacking

Abstract-Vertical stacking of banyan networks has been an attractive architecture to construct optical switching networks due to its small depth, absolute signal loss uniformity and good fault tolerance property. Recently, F.K.Hwang extended the study of banyan-based networks to the general f -cast case, which covers the unicast (f = 1) and multicast (f = N ) as special cases. In this paper, we study the blocking probability of f -cast optical banyan networks under crosstalk-free constraint. It is expected that the proposed probability model can be used to dimension such an f -cast network and achieve a graceful tradeoff between hardware cost and blocking probability

Design techniques to enhance low-power wireless communication soc with reconfigurability and wake up radio

Nowadays, Internet of things applications are increasing, and each end-node has more demanding requirements such as energy efficiency and speed. The thesis proposes a heterogeneous elaboration unit for smart power applications, that consists of an ultra-low-power microcontroller coupled with a small (around 1k equivalent gates) soft-core of embedded FPGA. This digital system is implemented in 90-nm BCD technology of STMicroelectronics, and through the analysis presented in this thesis proves to have good performance in terms of power consumption and latency. The idea is to increase the system performance exploiting the embedded FPGA to managing smart power tasks. For the intended applications, a remarkable computational load is not required, it is just required the implementation of simple finite state machines, since they are event-driven applications. In this way, while the microcontroller deals with other system computations such as high-level communications, the eFPGA can efficiently manage smart power applications. An added value of the proposed elaboration unit is that a soft-core approach is applied to the whole digital system including the eFPGA, and hence, it is portable to different technologies. On the other hand, the configurability improvement has a straightforward drawback of about a 20–27% area overhead. The eFPGA usage to manage smart power applications, allows the system to reduce the required energy per task from about 400 to around 800 times compared to a processor implementation. The eFPGA utilization improves also the latency performance of the system reaching from 8 to 145 times less latency in terms of clock cycles. The thesis also introduces the architecture of a nano-watt wake-up radio integrated circuit implemented in 90-nm BCD technology of STMicroelectronics. The wake-up radio is an auxiliary always-on radio for medium-range applications that allows the IoT end-nodes to drastically reduce the power consumption during the node idle-listening communication phase

Performance study of multirate circuit switching in quantized clos network.

by Vincent Wing-Shing Tse.Thesis submitted in: December 1997.Thesis (M.Phil.)--Chinese University of Hong Kong, 1998.Includes bibliographical references (leaves 62-[64]).Abstract also in Chinese.Chapter 1 --- Introduction --- p.1Chapter 2 --- Principles of Multirate Circuit Switching in Quantized Clos Network --- p.10Chapter 2.1 --- Formulation of Multirate Circuit Switching --- p.11Chapter 2.2 --- Call Level Routing in Quantized Clos Network --- p.12Chapter 2.3 --- Cell Level Routing in Quantized Clos Network --- p.16Chapter 2.3.1 --- Traffic Behavior in ATM Network --- p.17Chapter 2.3.2 --- Time Division Multiplexing in Multirate Circuit Switching and Cell-level Switching in ATM Network --- p.19Chapter 2.3.3 --- Cell Transmission Scheduling --- p.20Chapter 2.3.4 --- Capacity Allocation and Route Assignment at Cell-level --- p.29Chapter 3 --- Performance Evaluation of Different Implementation Schemes --- p.31Chapter 3.1 --- Global Control and Distributed Switching --- p.32Chapter 3.2 --- Implementation Schemes of Quantized Clos Network --- p.33Chapter 3.2.1 --- Classification of Switch Modules --- p.33Chapter 3.2.2 --- Bufferless Switch Modules Construction Scheme --- p.38Chapter 3.2.3 --- Buffered Switch Modules Construction Scheme --- p.42Chapter 3.3 --- Complexity Comparison --- p.44Chapter 3.4 --- Delay Performance of The Two Implementation Schemes --- p.47Chapter 3.4.1 --- Assumption --- p.47Chapter 3.4.2 --- Simulation Result --- p.50Chapter 4 --- Conclusions --- p.59Bibliography --- p.6

Analyzing Traffic and Multicast Switch Issues in an ATM Network.

This dissertation attempts to solve two problems related to an ATM network. First, we consider packetized voice and video sources as the incoming traffic to an ATM multiplexer and propose modeling methods for both individual and aggregated traffic sources. These methods are, then, used to analyze performance parameters such as buffer occupancy, cell loss probability, and cell delay. Results, thus obtained, for different buffer sizes and number of voice and video sources are analyzed and compared with those generated from existing techniques. Second, we study the priority handling feature for time critical services in an ATM multicast switch. For this, we propose a non-blocking copy network and priority handling algorithms. We, then, analyze the copy network using an analytical method and simulation. The analysis utilizes both priority and non-priority cells for two different output reservation schemes. The performance parameters, based on cell delay, delay jitter, and cell loss probability, are studied for different buffer sizes and fan-outs under various input traffic loads. Our results show that the proposed copy network provides a better performance for the priority cells while the performance for the non-priority cells is slightly inferior in comparison with the scenario when the network does not consider priority handling. We also study the fault-tolerant behavior of the copy network, specially for the broadcast banyan network subsection, and present a routing scheme considering the non-blocking property under a specific pattern of connection assignments. A fault tolerant characteristic can be quantified using the full access probability. The computation of the full access probability for a general network is known to be NP-hard. We, therefore, provide a new bounding technique utilizing the concept of minimal cuts to compute full access probability of the copy network. Our study for the fault-tolerant multi-stage interconnection network having either an extra stage or chaining shows that the proposed technique provides tighter bounds as compared to those given by existing approaches. We also apply our bounding method to compute full access probability of the fault-tolerant copy network

Switching techniques for broadband ISDN

The properties of switching techniques suitable for use in broadband networks have been investigated. Methods for evaluating the performance of such switches have been reviewed. A notation has been introduced to describe a class of binary self-routing networks. Hence a technique has been developed for determining the nature of the equivalence between two networks drawn from this class. The necessary and sufficient condition for two packets not to collide in a binary self-routing network has been obtained. This has been used to prove the non-blocking property of the Batcher-banyan switch. A condition for a three-stage network with channel grouping and link speed-up to be nonblocking has been obtained, of which previous conditions are special cases. A new three-stage switch architecture has been proposed, based upon a novel cell-level algorithm for path allocation in the intermediate stage of the switch. The algorithm is suited to hardware implementation using parallelism to achieve a very short execution time. An array of processors is required to implement the algorithm The processor has been shown to be of simple design. It must be initialised with a count representing the number of cells requesting a given output module. A fast method has been described for performing the request counting using a non-blocking binary self-routing network. Hardware is also required to forward routing tags from the processors to the appropriate data cells, when they have been allocated a path through the intermediate stage. A method of distributing these routing tags by means of a non-blocking copy network has been presented. The performance of the new path allocation algorithm has been determined by simulation. The rate of cell loss can increase substantially in a three-stage switch when the output modules are non-uniformly loaded. It has been shown that the appropriate use of channel grouping in the intermediate stage of the switch can reduce the effect of non-uniform loading on performance

A rearrangeable nonblocking multi-log2N multicast switching network

A new rearrangeable nonblocking photonic multi- log2N network DM(N) is introduced. It is shown that DM(N) network simultaneously possesses many good properties, including those of existing rearrangeable nonblocking multi-log2 N networks and new ones such as O(logN)-time fast parallel self-routing and nonblocking multiple-multicast.© IEE