7,031 research outputs found
Behavioral Modelling of Digital Devices Via Composite Local-Linear State-Space Relations
This paper addresses the generation of accurate and efficient behavioral models of digital ICs. The proposed approach is based on the approximation of the device port characteristics by means of composite local linear state-space relations whose parameters can effectively be estimated from device port transient responses via well-established system identification techniques. The proposedmodels have been proven to overcome some inherent limitations of the state-of-the-art models used so far, and they can effectively be implemented in any commercial tool as Simulation Program with Integrated Circuit Emphasis (SPICE) subcircuits or VHDL-AMS hardware descriptions. A systematic study of the performances of the proposed state-space models is carried out on a synthetic test device. The effectiveness of the proposed approach has been demonstrated on a real application problem involving commercial devices and a data link of a mobile phon
Parametric Macromodels of Differential Drivers and Receivers
This paper addresses the modeling of differential drivers and receivers for the analog simulation of high-speed interconnection systems. The proposed models are based on mathematical expressions, whose parameters can be estimated from the transient responses of the modeled devices. The advantages of this macromodeling approach are: improved accuracy with respect to models based on simplified equivalent circuits of devices; improved numerical efficiency with respect to detailed transistor-level models of devices; hiding of the internal structure of devices; straightforward circuit interpretation; or implementations in analog mixed-signal simulators. The proposed methodology is demonstrated on example devices and is applied to the prediction of transient waveforms and eye diagrams of a typical low-voltage differential signaling (LVDS) data link
Locally-Stable Macromodels of Integrated Digital Devices for Multimedia Applications
This paper addresses the development of accurate and efficient behavioral models of digital integrated circuits for the assessment of high-speed systems. Device models are based on suitable parametric expressions estimated from port transient responses and are effective at system level, where the quality of functional signals and the impact of supply noise need to be simulated. A potential limitation of some state-of-the-art modeling techniques resides in hidden instabilities manifesting themselves in the use of models, without being evident in the building phase of the same models. This contribution compares three recently-proposed model structures, and selects the local-linear state-space modeling technique as an optimal candidate for the signal integrity assessment of data links. In fact, this technique combines a simple verification of the local stability of models with a limited model size and an easy implementation in commercial simulation tools. An application of the proposed methodology to a real problem involving commercial devices and a data-link of a wireless device demonstrates the validity of this approac
Parametric Macromodels of Differential Drivers with Pre-Emphasis
This paper discusses the extraction of behavioral models of differential drivers with pre-emphasis for the assessment of signal integrity and electromagnetic compatibility effects in multigigabit data transmission systems. A suitable model structure is derived and the procedure for its estimation from port transient waveforms is illustrated. The proposed methodology is an extension of the macromodeling based on parametric relations applied to plain differential drivers. The obtained models preserve the accuracy and efficiency strengths of behavioral parametric macromodels for conventional devices. A realistic application example involving a high-speed communication path and a 3.125 Gb/s commercial driver model with pre-emphasis is presente
Limits on Fundamental Limits to Computation
An indispensable part of our lives, computing has also become essential to
industries and governments. Steady improvements in computer hardware have been
supported by periodic doubling of transistor densities in integrated circuits
over the last fifty years. Such Moore scaling now requires increasingly heroic
efforts, stimulating research in alternative hardware and stirring controversy.
To help evaluate emerging technologies and enrich our understanding of
integrated-circuit scaling, we review fundamental limits to computation: in
manufacturing, energy, physical space, design and verification effort, and
algorithms. To outline what is achievable in principle and in practice, we
recall how some limits were circumvented, compare loose and tight limits. We
also point out that engineering difficulties encountered by emerging
technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl
A Reactive and Cycle-True IP Emulator for MPSoC Exploration
The design of MultiProcessor Systems-on-Chip
(MPSoC) emphasizes intellectual-property (IP)-based
communication-centric approaches. Therefore, for the optimization
of the MPSoC interconnect, the designer must develop
traffic models that realistically capture the application behavior
as executing on the IP core. In this paper, we introduce a
Reactive IP Emulator (RIPE) that enables an effective emulation
of the IP-core behavior in multiple environments, including bitand
cycle-true simulation. The RIPE is built as a multithreaded
abstract instruction-set processor, and it can generate reactive
traffic patterns. We compare the RIPE models with cycle-true
functional simulation of complex application behavior (tasksynchronization,
multitasking, and input/output operations).
Our results demonstrate high-accuracy and significant speedups.
Furthermore, via a case study, we show the potential use of the
RIPE in a design-space-exploration context
Overview of Swallow --- A Scalable 480-core System for Investigating the Performance and Energy Efficiency of Many-core Applications and Operating Systems
We present Swallow, a scalable many-core architecture, with a current
configuration of 480 x 32-bit processors.
Swallow is an open-source architecture, designed from the ground up to
deliver scalable increases in usable computational power to allow
experimentation with many-core applications and the operating systems that
support them.
Scalability is enabled by the creation of a tile-able system with a
low-latency interconnect, featuring an attractive communication-to-computation
ratio and the use of a distributed memory configuration.
We analyse the energy and computational and communication performances of
Swallow. The system provides 240GIPS with each core consuming 71--193mW,
dependent on workload. Power consumption per instruction is lower than almost
all systems of comparable scale.
We also show how the use of a distributed operating system (nOS) allows the
easy creation of scalable software to exploit Swallow's potential. Finally, we
show two use case studies: modelling neurons and the overlay of shared memory
on a distributed memory system.Comment: An open source release of the Swallow system design and code will
follow and references to these will be added at a later dat
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Chippe : a system for constraint driven behavioral synthesis
This report describes the Chippe system, gives some background previous work and describes several sample design runs of the system. Also presented are the sources of the design tradeoffs used by Chippe, and overview of the internal design model, and experiences using the system
Delay Measurements and Self Characterisation on FPGAs
This thesis examines new timing measurement methods for self delay characterisation of Field-Programmable Gate Arrays (FPGAs) components and delay measurement of complex circuits
on FPGAs. Two novel measurement techniques based on analysis of a circuit's output failure
rate and transition probability is proposed for accurate, precise and efficient measurement of
propagation delays. The transition probability based method is especially attractive, since
it requires no modifications in the circuit-under-test and requires little hardware resources,
making it an ideal method for physical delay analysis of FPGA circuits.
The relentless advancements in process technology has led to smaller and denser transistors
in integrated circuits. While FPGA users benefit from this in terms of increased hardware
resources for more complex designs, the actual productivity with FPGA in terms of timing
performance (operating frequency, latency and throughput) has lagged behind the potential
improvements from the improved technology due to delay variability in FPGA components
and the inaccuracy of timing models used in FPGA timing analysis. The ability to measure
delay of any arbitrary circuit on FPGA offers many opportunities for on-chip characterisation
and physical timing analysis, allowing delay variability to be accurately tracked and variation-aware optimisations to be developed, reducing the productivity gap observed in today's FPGA
designs.
The measurement techniques are developed into complete self measurement and characterisation platforms in this thesis, demonstrating their practical uses in actual FPGA hardware for
cross-chip delay characterisation and accurate delay measurement of both complex combinatorial and sequential circuits, further reinforcing their positions in solving the delay variability
problem in FPGAs
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