Multistage Packet-Switching Fabrics for Data Center Networks

Recent applications have imposed stringent requirements within the Data Center Network (DCN) switches in terms of scalability, throughput and latency. In this thesis, the architectural design of the packet-switches is tackled in different ways to enable the expansion in both the number of connected endpoints and traffic volume. A cost-effective Clos-network switch with partially buffered units is proposed and two packet scheduling algorithms are described. The first algorithm adopts many simple and distributed arbiters, while the second approach relies on a central arbiter to guarantee an ordered packet delivery. For an improved scalability, the Clos switch is build using a Network-on-Chip (NoC) fabric instead of the common crossbar units. The Clos-UDN architecture made with Input-Queued (IQ) Uni-Directional NoC modules (UDNs) simplifies the input line cards and obviates the need for the costly Virtual Output Queues (VOQs). It also avoids the need for complex, and synchronized scheduling processes, and offers speedup, load balancing, and good path diversity. Under skewed traffic, a reliable micro load-balancing contributes to boosting the overall network performance. Taking advantage of the NoC paradigm, a wrapped-around multistage switch with fully interconnected Central Modules (CMs) is proposed. The architecture operates with a congestion-aware routing algorithm that proactively distributes the traffic load across the switching modules, and enhances the switch performance under critical packet arrivals. The implementation of small on-chip buffers has been made perfectly feasible using the current technology. This motivated the implementation of a large switching architecture with an Output-Queued (OQ) NoC fabric. The design merges assets of the output queuing, and NoCs to provide high throughput, and smooth latency variations. An approximate analytical model of the switch performance is also proposed. To further exploit the potential of the NoC fabrics and their modularity features, a high capacity Clos switch with Multi-Directional NoC (MDN) modules is presented. The Clos-MDN switching architecture exhibits a more compact layout than the Clos-UDN switch. It scales better and faster in port count and traffic load. Results achieved in this thesis demonstrate the high performance, expandability and programmability features of the proposed packet-switches which makes them promising candidates for the next-generation data center networking infrastructure

Multistage Packet-Switching Fabrics for Data Center Networks

Recent applications have imposed stringent requirements within the Data Center Network (DCN) switches in terms of scalability, throughput and latency. In this thesis, the architectural design of the packet-switches is tackled in different ways to enable the expansion in both the number of connected endpoints and traffic volume. A cost-effective Clos-network switch with partially buffered units is proposed and two packet scheduling algorithms are described. The first algorithm adopts many simple and distributed arbiters, while the second approach relies on a central arbiter to guarantee an ordered packet delivery. For an improved scalability, the Clos switch is build using a Network-on-Chip (NoC) fabric instead of the common crossbar units. The Clos-UDN architecture made with Input-Queued (IQ) Uni-Directional NoC modules (UDNs) simplifies the input line cards and obviates the need for the costly Virtual Output Queues (VOQs). It also avoids the need for complex, and synchronized scheduling processes, and offers speedup, load balancing, and good path diversity. Under skewed traffic, a reliable micro load-balancing contributes to boosting the overall network performance. Taking advantage of the NoC paradigm, a wrapped-around multistage switch with fully interconnected Central Modules (CMs) is proposed. The architecture operates with a congestion-aware routing algorithm that proactively distributes the traffic load across the switching modules, and enhances the switch performance under critical packet arrivals. The implementation of small on-chip buffers has been made perfectly feasible using the current technology. This motivated the implementation of a large switching architecture with an Output-Queued (OQ) NoC fabric. The design merges assets of the output queuing, and NoCs to provide high throughput, and smooth latency variations. An approximate analytical model of the switch performance is also proposed. To further exploit the potential of the NoC fabrics and their modularity features, a high capacity Clos switch with Multi-Directional NoC (MDN) modules is presented. The Clos-MDN switching architecture exhibits a more compact layout than the Clos-UDN switch. It scales better and faster in port count and traffic load. Results achieved in this thesis demonstrate the high performance, expandability and programmability features of the proposed packet-switches which makes them promising candidates for the next-generation data center networking infrastructure

Modelos analíticos para la evaluación de mecanismos de control de tráfico en redes ATM

Se presentan una serie de modelos analíticos que son de utilidad para la evaluación de mecanismos de control de tráfico en redes digitales de servicios integrados de alta velocidad que usan conmutación de paquetes. En concreto se estudia el caso de redes ATM (Asynchronous Transfer Mode).Por un lado se ha desarrollado un modelo para evaluar la perturbación que se introduce al multiplexar un flujo individual de tasa constante que tráfico a ráfagas. Por otro lado, se ha estudiado mecanismos que permiten discriminar entre células ATM que ocupan un buffer de memoria en un mutiplexor o conmutador, estableciendo una prioridad de pérdidas.En el desarrollo de los modelos se ha tenido en cuenta las correlaciones que aparecen en los flujos de tráfico de dichas redes. Para ello se han usado modelos markovianos, en los que el estado de una cadena de Markov permite caracterizar la intensidad del tráfico. Los modelos de colas resultantes se han resuelto usando la metodología de análisis matricial de colas desarrollada principalmente por M. F. Neuts y modelos de aproximación de fluido.We study analytical models for the performance evaluation of traffic control mechanisms in high-speed packet switching digital integrated services networks. In particular, we focus our study on the case of ATM networks.The main contributions of this work are two: (i) An analytical model to evaluate the Cell Delay Variation introduced on a CBR flow, and (ii) several analytical models to study Space Priority mechanism, which introduce a priority among cells in the occupancy of multiplexers and switch buffers.These models take into account the traffic correlation present in this type of networks. We have used markovian models, where each state of the Markov chain characterizes the intensity of the traffic. The obtained queueing models where solved using the Matrix Analysis methodology developed by M. F. Neuts, and a fluid-flow approximation