216 research outputs found
A SAT approach to the initial mapping problem in SWAP gate insertion for commuting gates
Most quantum circuits require SWAP gate insertion to run on quantum hardware
with limited qubit connectivity. A promising SWAP gate insertion method for
blocks of commuting two-qubit gates is a predetermined swap strategy which
applies layers of SWAP gates simultaneously executable on the coupling map. A
good initial mapping for the swap strategy reduces the number of required swap
gates. However, even when a circuit consists of commuting gates, e.g., as in
the Quantum Approximate Optimization Algorithm (QAOA) or trotterized
simulations of Ising Hamiltonians, finding a good initial mapping is a hard
problem. We present a SAT-based approach to find good initial mappings for
circuits with commuting gates transpiled to the hardware with swap strategies.
Our method achieves a 65% reduction in gate count for random three-regular
graphs with 500 nodes. In addition, we present a heuristic approach that
combines the SAT formulation with a clustering algorithm to reduce large
problems to a manageable size. This approach reduces the number of swap layers
by 25% compared to both a trivial and random initial mapping for a random
three-regular graph with 1000 nodes. Good initial mappings will therefore
enable the study of quantum algorithms, such as QAOA and Ising Hamiltonian
simulation applied to sparse problems, on noisy quantum hardware with several
hundreds of qubits.Comment: 7 page
Transistor-Level Layout of Integrated Circuits
In this dissertation, we present the toolchain BonnCell and its underlying algorithms. It has been developed in close cooperation with the IBM Corporation and automatically generates the geometry for functional groups of 2 to approximately 50 transistors. Its input consists of a set of transistors, including properties like their sizes and their types, a specification of their connectivity, and parameters to flexibly control the technological framework as well as the algorithms' behavior. Using this data, the tool computes a detailed geometric realization of the circuit as polygonal shapes on 16 layers. To this end, a placement routine configures the transistors and arranges them in the plane, which is the main subject of this thesis. Subsequently, a routing engine determines wires connecting the transistors to ensure the circuit's desired functionality. We propose and analyze a family of algorithms that arranges sets of transistors in the plane such that a multi-criteria target function is optimized. The primary goal is to obtain solutions that are as compact as possible because chip area is a valuable resource in modern techologies. In addition to the core algorithms we formulate variants that handle particularly structured instances in a suitable way. We will show that for 90% of the instances in a representative test bed provided by IBM, BonnCell succeeds to generate fully functional layouts including the placement of the transistors and a routing of their interconnections. Moreover, BonnCell is in wide use within IBM's groups that are concerned with transistor-level layout - a task that has been performed manually before our automation was available. Beyond the processing of isolated test cases, two large-scale examples for applications of the tool in the industry will be presented: On the one hand the initial design phase of a large SRAM unit required only half of the expected 3 month period, on the other hand BonnCell could provide valuable input aiding central decisions in the early concept phase of the new 14 nm technology generation
Effective algorithms and protocols for wireless networking: a topological approach
Much research has been done on wireless sensor networks. However, most protocols
and algorithms for such networks are based on the ideal model Unit Disk Graph
(UDG) model or do not assume any model. Furthermore, many results assume the
knowledge of location information of the network. In practice, sensor networks often
deviate from the UDG model significantly. It is not uncommon to observe stable long
links that are more than five times longer than unstable short links in real wireless
networks. A more general network model, the quasi unit-disk graph (quasi-UDG)
model, captures much better the characteristics of wireless networks. However, the
understanding of the properties of general quasi-UDGs has been very limited, which
is impeding the design of key network protocols and algorithms.
In this dissertation we study the properties for general wireless sensor networks
and develop new topological/geometrical techniques for wireless sensor networking.
We assume neither the ideal UDG model nor the location information of the nodes.
Instead we work on the more general quasi-UDG model and focus on figuring out
the relationship between the geometrical properties and the topological properties of
wireless sensor networks. Based on such relationships we develop algorithms that can
compute useful substructures (planar subnetworks, boundaries, etc.). We also present direct applications of the properties and substructures we constructed including routing,
data storage, topology discovery, etc.
We prove that wireless networks based on quasi-UDG model exhibit nice properties
like separabilities, existences of constant stretch backbones, etc. We develop
efficient algorithms that can obtain relatively dense planar subnetworks for wireless
sensor networks. We also present efficient routing protocols and balanced data storage
scheme that supports ranged queries.
We present algorithmic results that can also be applied to other fields (e.g., information
management). Based on divide and conquer and improved color coding
technique, we develop algorithms for path, matching and packing problem that significantly
improve previous best algorithms. We prove that it is unlikely for certain
problems in operation science and information management to have any relatively
effective algorithm or approximation algorithm for them
Timing-Constrained Global Routing with Buffered Steiner Trees
This dissertation deals with the combination of two key problems that arise in the physical design of computer chips: global routing and buffering. The task of buffering is the insertion of buffers and inverters into the chip's netlist to speed-up signal delays and to improve electrical properties of the chip. Insertion of buffers and inverters goes alongside with construction of Steiner trees that connect logical sources with possibly many logical sinks and have buffers and inverters as parts of these connections. Classical global routing focuses on packing Steiner trees within the limited routing space. Buffering and global routing have been solved separately in the past. In this thesis we overcome the limitations of the classical approaches by considering the buffering problem as a global, multi-objective problem. We study its theoretical aspects and propose algorithms which we implement in the tool BonnRouteBuffer for timing-constrained global routing with buffered Steiner trees. At its core, we propose a new theoretically founded framework to model timing constraints inherently within global routing. As most important sub-task we have to compute a buffered Steiner tree for a single net minimizing the sum of prices for delays, routing congestion, placement congestion, power consumption, and net length. For this sub-task we present a fully polynomial time approximation scheme to compute an almost-cheapest Steiner tree with a given routing topology and prove that an exact algorithm cannot exist unless P=NP. For topology computation we present a bicriteria approximation algorithm that bounds both the geometric length and the worst slack of the topology. To improve the practical results we present many heuristic modifications, speed-up- and post-optimization techniques for buffered Steiner trees. We conduct experiments on challenging real-world test cases provided by our cooperation partner IBM to demonstrate the quality of our tool. Our new algorithm could produce better solutions with respect to both timing and routability. After post-processing with gate sizing and Vt-assignment, we can even reduce the power consumption on most instances. Overall, our results show that our tool BonnRouteBuffer for timing-constrained global routing is superior to industrial state-of-the-art tools
Combinatorial Optimization
This report summarizes the meeting on Combinatorial Optimization where new and promising developments in the field were discussed. Th
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