Fabric defect detection using the wavelet transform in an ARM processor

Small devices used in our day life are constructed with powerful architectures that can be used for industrial applications when requiring portability and communication facilities. We present in this paper an example of the use of an embedded system, the Zeus epic 520 single board computer, for defect detection in textiles using image processing. We implement the Haar wavelet transform using the embedded visual C++ 4.0 compiler for Windows CE 5. The algorithm was tested for defect detection using images of fabrics with five types of defects. An average of 95% in terms of correct defect detection was obtained, achieving a similar performance than using processors with float point arithmetic calculations

Real-time portable system for fabric defect detection using an ARM processor

Modern textile industry seeks to produce textiles as little defective as possible since the presence of defects can decrease the final price of products from 45% to 65%. Automated visual inspection (AVI) systems, based on image analysis, have become an important alternative for replacing traditional inspections methods that involve human tasks. An AVI system gives the advantage of repeatability when implemented within defined constrains, offering more objective and reliable results for particular tasks than human inspection. Costs of automated inspection systems development can be reduced using modular solutions with embedded systems, in which an important advantage is the low energy consumption. Among the possibilities for developing embedded systems, the ARM processor has been explored for acquisition, monitoring and simple signal processing tasks. In a recent approach we have explored the use of the ARM processor for defects detection by implementing the wavelet transform. However, the computation speed of the preprocessing was not yet sufficient for real time applications. In this approach we significantly improve the preprocessing speed of the algorithm, by optimizing matrix operations, such that it is adequate for a real time application. The system was tested for defect detection using different defect types. The paper is focused in giving a detailed description of the basis of the algorithm implementation, such that other algorithms may use of the ARM operations for fast implementations

A Vlsi architecture for lifting-based wavelet packet transform in fingerprint image compression

FBI uses a technique called Wavelet Scalar Quantization (WSQ), a wavelet packet transform (WPT) based method, to compress its fingerprint images. Though many VLSI architectures have been proposed for wavelet transform in the literature, it is not the case for the WPT. In this thesis, a VLSI architecture capable of computing the WPT is presented for application of WSQ. In the proposed architecture, Lifting Scheme (LS) is used to generate wavelets instead of the traditional convolution filter-bank (FB) specified in original standard. A comparative study between LS and FB shows that quality of images transformed by LS is completely acceptable (with 30dB∼40dB PSNR at a target bit rate of 0.75dpp) while fewer operations required. In particular, to compare with FB, the hardware consumption, for our WSQ application, is reduced to half due to the LS. Moreover, this architecture can be easily configured to compute any required WPT application

DCT Implementation on GPU

There has been a great progress in the field of graphics processors. Since, there is no rise in the speed of the normal CPU processors; Designers are coming up with multi-core, parallel processors. Because of their popularity in parallel processing, GPUs are becoming more and more attractive for many applications. With the increasing demand in utilizing GPUs, there is a great need to develop operating systems that handle the GPU to full capacity. GPUs offer a very efficient environment for many image processing applications. This thesis explores the processing power of GPUs for digital image compression using Discrete cosine transform

Optimization of 3-D Wavelet Decomposition on Multiprocessors

In this work we discuss various ideas for the optimization of 3-D wavelet/subband decomposition on shared memory MIMD computers. We theoretically evaluate the characteristics of these approaches and verify the results on parallel computers. Experimental results are conducted on a shared memory as well as a virtual shared memory architecture