A General Framework for Analyzing, Characterizing, and Implementing Spectrally Modulated, Spectrally Encoded Signals

Fourth generation (4G) communications will support many capabilities while providing universal, high speed access. One potential enabler for these capabilities is software defined radio (SDR). When controlled by cognitive radio (CR) principles, the required waveform diversity is achieved via a synergistic union called CR-based SDR. Research is rapidly progressing in SDR hardware and software venues, but current CR-based SDR research lacks the theoretical foundation and analytic framework to permit efficient implementation. This limitation is addressed here by introducing a general framework for analyzing, characterizing, and implementing spectrally modulated, spectrally encoded (SMSE) signals within CR-based SDR architectures. Given orthogonal frequency division multiplexing (OFDM) is a 4G candidate signal, OFDM-based signals are collectively classified as SMSE since modulation and encoding are spectrally applied. The proposed framework provides analytic commonality and unification of SMSE signals. Applicability is first shown for candidate 4G signals, and resultant analytic expressions agree with published results. Implementability is then demonstrated in multiple coexistence scenarios via modeling and simulation to reinforce practical utility

Reconfigurable cores for wireless appliances: Turbo codes

The thesis introduces the subject of Turbo codes, highlighting the motivation behind their inclusion in international standards. Particular attention is given to the cdma2000 and UMTS third generation mobile telephony standards. Both the technical and commercial advantages/disadvantages of implementing Turbo codes in a Field Programmable Gate Array (FPGA) based system are discussed. The subject of third generation mobile technology is also discussed, this includes an introduction to spread spectrum and rake receivers. The commercial relevance of all projects conducted is discussed. These projects allowed the sponsoring company to highlight the advantages of using FPGAs in third generation mobile base stations. A novel system for testing forward error correction (FEC) codes is presented. Results obtained are shown and discussed. A novel parameterisable Turbo decoder will also be highlighted. The decoder in question allows the user to specify certain criteria that can be used to control the memory used by the decoder and its latency. A novel hardware architecture for Turbo decoders is proposed, as is a unique channel variance value that optimises a cdma2000 Turbo decoder. Other subjects covered are Duo-Binary Turbo codes. Turbo decoder hardware architectures and how to calculate the input values to Turbo decoders

Downlink W-CDMA performance analysis and receiver implmentation on SC140 Motorola DSP

High data rate applications are the trend in today's wireless technology. W-CDMA standard was designed to support such high data rates of up to 3.84 Mcps. The main purpose of this research was to analyze the feasibility of a fixed-point implementation of the W-CDMA downlink receiver algorithm on a general-purpose digital signal processor (StarCore SC140 by Motorola). The very large instruction word architecture of SC140 core is utilized to generate optimal implementation, to meet the real time timing requirements of the algorithm. The other main aim of this work was to study and evaluate the performance of the W-CDMA downlink structure with incorporated space-time transmit diversity. The effect of the channel estimation algorithm used was extensively studied too

On the economic and technological forces shaping mobile transceiver architecture

Thesis (S.M.)--Massachusetts Institute of Technology, System Design and Management Program, 2009.Includes bibliographical references (p. 166-168).The thesis examines the evolution of mobile transceiver architecture using the management framework pioneered by Carliss Baldwin and Kim Clark. The thesis begins with an introduction and an overview of the wireless communication value network. The author subsequently distills the salient aspects of the Baldwin and Clark management framework predicated on bottleneck analysis, modularity, and return on invested capital. The prominence of bottleneck analysis motivates a technical chapter that summarizes the bottlenecks relevant to all wireless communication systems, namely data rate, error rate, and battery life. A brief chapter discussing the dominant wireless communication network architecture, TDMA and CDMA, corroborates the bottleneck analysis and effectively assigns the error rate and battery life bottlenecks to the handset ODM and supplier layers of the value network. With a clear vision of the competitive bottlenecks, the evolution of transceiver architecture is presented in the context of the aforementioned management framework. Through this analysis, design power is shown to have passed from handset ODMs to integrated circuit suppliers. A noteworthy byproduct of the analysis is the genesis of the bottleneck tree whereby new layers of bottlenecks are emergent upon a firm's selection of a particular design architecture that targets the strategic bottleneck layer. Finally, the thesis is concluded with a summary of the ground covered and the author's opinions of how the architecture may yet evolve and the future nature of the competitive landscape.by Christopher A. Aden.S.M

Adaptive PN code synchronisation in DS-CDMA systems

Spread Spectrum (SS) communication, initially designed for military applications, is now the basis for many of today's advanced communications systems such as Code Division Multiple Access (CDMA), Global Positioning System (GPS), Wireless Local Loop (WLL) , etc. For effective communication to take place in systems using SS modulation, the Pseudo-random Noise (PN) code used at the receiver to despread the received signal must be identical and be synchronised with the PN code that was used to spread the signal at the transmitter. Synchronisation is done in two steps: coarse synchronisation or acquisition, and fine synchronisation or tracking. Acquisition involves obtaining a coarse estimate of the phase shift between the transmitted PN code and that at the receiver so that the received PN code will be aligned or synchronised with the locally generated PN code. After acquisition, tracldng is now done which involves maintaining the alignment of the two PN codes. This thesis presents results of the research calTied out on a proposed adaptive PN code acquisition circuit designed to improve the synchronisation process in Direct Sequence CDMA (DS-CDMA) systems. The acquisition circuit is implemented using a Matched Filter (MF) for the correlation operation and the threshold setting device is an adaptive processor known as the Cell Averaging Constant False Alarm Rate (CA-CFAR) processor. It is a double dwell acquisition circuit where the second dwell is implemented by Post Detection Integration (PDI). Depending on the application, PDI can be used to mitigate the effect of frequency offset in non-coherent detectors and/or in the implementation of multiple dwell acquisition systems. Equations relating the performance measures - the probability of false alarm (Pra ), the probability of detection (P d) and the mean acquisition time (E {Tacq}) - of the circuit are deri ved. Monte Carlo simulation was used for the independent validation of the theoretical results obtained, and the strong agreement between these results shows the accuracy of the derived equations for the proposed circuit. Due to the combination of PDI and CA-CFAR processor in the implementation of the circuit, results obtained show that it can provide a good measure of robustness to frequency offset and noise power variations in mobile environment, consequently leading to improved acquisition time performance. The complete synchronisation circuit is realised by using this circuit in conjunction with a conventional code tracking circuit. Therefore, a study of a Non-coherent Delay-Locked Loop (NDLL) code tracking circuit is also calTied out.EThOS - Electronic Theses Online ServiceGBUnited Kingdo

Adaptive PN code synchronisation in DS-CDMA systems.

Spread Spectrum (SS) communication, initially designed for military applications, isnow the basis for many of today's advanced communications systems such as CodeDivision Multiple Access (CDMA), Global Positioning System (GPS), Wireless LocalLoop (WLL) , etc. For effective communication to take place in systems using SSmodulation, the Pseudo-random Noise (PN) code used at the receiver to despread thereceived signal must be identical and be synchronised with the PN code that was used tospread the signal at the transmitter. Synchronisation is done in two steps: coarsesynchronisation or acquisition, and fine synchronisation or tracking. Acquisitioninvolves obtaining a coarse estimate of the phase shift between the transmitted PN codeand that at the receiver so that the received PN code will be aligned or synchronisedwith the locally generated PN code. After acquisition, tracldng is now done whichinvolves maintaining the alignment of the two PN codes.This thesis presents results of the research calTied out on a proposed adaptive PN codeacquisition circuit designed to improve the synchronisation process in Direct SequenceCDMA (DS-CDMA) systems. The acquisition circuit is implemented using a MatchedFilter (MF) for the correlation operation and the threshold setting device is an adaptiveprocessor known as the Cell Averaging Constant False Alarm Rate (CA-CFAR)processor. It is a double dwell acquisition circuit where the second dwell isimplemented by Post Detection Integration (PDI). Depending on the application, PDIcan be used to mitigate the effect of frequency offset in non-coherent detectors and/or inthe implementation of multiple dwell acquisition systems. Equations relating theperformance measures - the probability of false alarm (Pra ), the probability of detection (P d) and the mean acquisition time (E {Tacq}) - of the circuit are deri ved. Monte Carlosimulation was used for the independent validation of the theoretical results obtained,and the strong agreement between these results shows the accuracy of the derivedequations for the proposed circuit. Due to the combination of PDI and CA-CFARprocessor in the implementation of the circuit, results obtained show that it can providea good measure of robustness to frequency offset and noise power variations in mobileenvironment, consequently leading to improved acquisition time performance. Thecomplete synchronisation circuit is realised by using this circuit in conjunction with aconventional code tracking circuit. Therefore, a study of a Non-coherent Delay-LockedLoop (NDLL) code tracking circuit is also calTied out