Floating-Gate Design and Linearization for Reconfigurable Analog Signal Processing

Analog and mixed-signal integrated circuits have found a place in modern electronics design as a viable alternative to digital pre-processing. With metrics that boast high accuracy and low power consumption, analog pre-processing has opened the door to low-power state-monitoring systems when it is utilized in place of a power-hungry digital signal-processing stage. However, the complicated design process required by analog and mixed-signal systems has been a barrier to broader applications. The implementation of floating-gate transistors has begun to pave the way for a more reasonable approach to analog design. Floating-gate technology has widespread use in the digital domain. Analog and mixed-signal use of floating-gate transistors has only become a rising field of study in recent years. Analog floating gates allow for low-power implementation of mixed-signal systems, such as the field-programmable analog array, while simultaneously opening the door to complex signal-processing techniques. The field-programmable analog array, which leverages floating-gate technologies, is demonstrated as a reliable replacement to signal-processing tasks previously only solved by custom design. Living in an analog world demands the constant use and refinement of analog signal processing for the purpose of interfacing with digital systems. This work offers a comprehensive look at utilizing floating-gate transistors as the core element for analog signal-processing tasks. This work demonstrates the floating gate\u27s merit in large reconfigurable array-driven systems and in smaller-scale implementations, such as linearization techniques for oscillators and analog-to-digital converters. A study on analog floating-gate reliability is complemented with a temperature compensation scheme for implementing these systems in ever-changing, realistic environments

Data Conversion Within Energy Constrained Environments

Within scientific research, engineering, and consumer electronics, there is a multitude of new discrete sensor-interfaced devices. Maintaining high accuracy in signal quantization while staying within the strict power-budget of these devices is a very challenging problem. Traditional paths to solving this problem include researching more energy-efficient digital topologies as well as digital scaling.;This work offers an alternative path to lower-energy expenditure in the quantization stage --- content-dependent sampling of a signal. Instead of sampling at a constant rate, this work explores techniques which allow sampling based upon features of the signal itself through the use of application-dependent analog processing. This work presents an asynchronous sampling paradigm, based off the use of floating-gate-enabled analog circuitry. The basis of this work is developed through the mathematical models necessary for asynchronous sampling, as well the SPICE-compatible models necessary for simulating floating-gate enabled analog circuitry. These base techniques and circuitry are then extended to systems and applications utilizing novel analog-to-digital converter topologies capable of leveraging the non-constant sampling rates for significant sample and power savings

A Novel Power-Efficient Wireless Multi-channel Recording System for the Telemonitoring of Electroencephalography (EEG)

This research introduces the development of a novel EEG recording system that is modular, batteryless, and wireless (untethered) with the supporting theoretical foundation in wireless communications and related design elements and circuitry. Its modular construct overcomes the EEG scaling problem and makes it easier for reconfiguring the hardware design in terms of the number and placement of electrodes and type of standard EEG system contemplated for use. In this development, portability, lightweight, and applicability to other clinical applications that rely on EEG data are sought. Due to printer tolerance, the 3D printed cap consists of 61 electrode placements. This recording capacity can however extend from 21 (as in the international 10-20 systems) up to 61 EEG channels at sample rates ranging from 250 to 1000 Hz and the transfer of the raw EEG signal using a standard allocated frequency as a data carrier. The main objectives of this dissertation are to (1) eliminate the need for heavy mounted batteries, (2) overcome the requirement for bulky power systems, and (3) avoid the use of data cables to untether the EEG system from the subject for a more practical and less restrictive setting. Unpredictability and temporal variations of the EEG input make developing a battery-free and cable-free EEG reading device challenging. Professional high-quality and high-resolution analog front ends are required to capture non-stationary EEG signals at microvolt levels. The primary components of the proposed setup are the wireless power transmission unit, which consists of a power amplifier, highly efficient resonant-inductive link, rectification, regulation, and power management units, as well as the analog front end, which consists of an analog to digital converter, pre-amplification unit, filtering unit, host microprocessor, and the wireless communication unit. These must all be compatible with the rest of the system and must use the least amount of power possible while minimizing the presence of noise and the attenuation of the recorded signal A highly efficient resonant-inductive coupling link is developed to decrease power transmission dissipation. Magnetized materials were utilized to steer electromagnetic flux and decrease route and medium loss while transmitting the required energy with low dissipation. Signal pre-amplification is handled by the front-end active electrodes. Standard bio-amplifier design approaches are combined to accomplish this purpose, and a thorough investigation of the optimum ADC, microcontroller, and transceiver units has been carried out. We can minimize overall system weight and power consumption by employing battery-less and cable-free EEG readout system designs, consequently giving patients more comfort and freedom of movement. Similarly, the solutions are designed to match the performance of medical-grade equipment. The captured electrical impulses using the proposed setup can be stored for various uses, including classification, prediction, 3D source localization, and for monitoring and diagnosing different brain disorders. All the proposed designs and supporting mathematical derivations were validated through empirical and software-simulated experiments. Many of the proposed designs, including the 3D head cap, the wireless power transmission unit, and the pre-amplification unit, are already fabricated, and the schematic circuits and simulation results were based on Spice, Altium, and high-frequency structure simulator (HFSS) software. The fully integrated head cap to be fabricated would require embedding the active electrodes into the 3D headset and applying current technological advances to miniaturize some of the design elements developed in this dissertation

Integrated Electronics for Wireless Imaging Microsystems with CMUT Arrays

Integration of transducer arrays with interface electronics in the form of single-chip CMUT-on-CMOS has emerged into the field of medical ultrasound imaging and is transforming this field. It has already been used in several commercial products such as handheld full-body imagers and it is being implemented by commercial and academic groups for Intravascular Ultrasound and Intracardiac Echocardiography. However, large attenuation of ultrasonic waves transmitted through the skull has prevented ultrasound imaging of the brain. This research is a prime step toward implantable wireless microsystems that use ultrasound to image the brain by bypassing the skull. These microsystems offer autonomous scanning (beam steering and focusing) of the brain and transferring data out of the brain for further processing and image reconstruction. The objective of the presented research is to develop building blocks of an integrated electronics architecture for CMUT based wireless ultrasound imaging systems while providing a fundamental study on interfacing CMUT arrays with their associated integrated electronics in terms of electrical power transfer and acoustic reflection which would potentially lead to more efficient and high-performance systems. A fully wireless architecture for ultrasound imaging is demonstrated for the first time. An on-chip programmable transmit (TX) beamformer enables phased array focusing and steering of ultrasound waves in the transmit mode while its on-chip bandpass noise shaping digitizer followed by an ultra-wideband (UWB) uplink transmitter minimizes the effect of path loss on the transmitted image data out of the brain. A single-chip application-specific integrated circuit (ASIC) is de- signed to realize the wireless architecture and interface with array elements, each of which includes a transceiver (TRX) front-end with a high-voltage (HV) pulser, a high-voltage T/R switch, and a low-noise amplifier (LNA). Novel design techniques are implemented in the system to enhance the performance of its building blocks. Apart from imaging capability, the implantable wireless microsystems can include a pressure sensing readout to measure intracranial pressure. To do so, a power-efficient readout for pressure sensing is presented. It uses pseudo-pseudo differential readout topology to cut down the static power consumption of the sensor for further power savings in wireless microsystems. In addition, the effect of matching and electrical termination on CMUT array elements is explored leading to new interface structures to improve bandwidth and sensitivity of CMUT arrays in different operation regions. Comprehensive analysis, modeling, and simulation methodologies are presented for further investigation.Ph.D

Holistic Optimization of Embedded Computer Vision Systems

Despite strong interest in embedded computer vision, the computational demands of Convolutional Neural Network (CNN) inference far exceed the resources available in embedded devices. Thankfully, the typical embedded device has a number of desirable properties that can be leveraged to significantly reduce the time and energy required for CNN inference. This thesis presents three independent and synergistic methods for optimizing embedded computer vision: 1) Reducing the time and energy needed to capture and preprocess input images by optimizing the image capture pipeline for the needs of CNNs rather than humans. 2) Exploiting temporal redundancy within incoming video streams to perform computationally cheap motion estimation and compensation in lieu of full CNN inference for the majority of frames. 3) Leveraging the sparsity of CNN activations within the frequency domain to significantly reduce the number of operations needed for inference. Collectively these techniques significantly reduce the time and energy needed for computer vision at the edge, enabling a wide variety of exciting new applications

A Construction Kit for Efficient Low Power Neural Network Accelerator Designs

Implementing embedded neural network processing at the edge requires efficient hardware acceleration that couples high computational performance with low power consumption. Driven by the rapid evolution of network architectures and their algorithmic features, accelerator designs are constantly updated and improved. To evaluate and compare hardware design choices, designers can refer to a myriad of accelerator implementations in the literature. Surveys provide an overview of these works but are often limited to system-level and benchmark-specific performance metrics, making it difficult to quantitatively compare the individual effect of each utilized optimization technique. This complicates the evaluation of optimizations for new accelerator designs, slowing-down the research progress. This work provides a survey of neural network accelerator optimization approaches that have been used in recent works and reports their individual effects on edge processing performance. It presents the list of optimizations and their quantitative effects as a construction kit, allowing to assess the design choices for each building block separately. Reported optimizations range from up to 10'000x memory savings to 33x energy reductions, providing chip designers an overview of design choices for implementing efficient low power neural network accelerators

Signal-Processing-Driven Integrated Circuits for Energy Constrained Microsystems.

The exponential growth in IC technology has enabled low-cost and increasingly capable wireless sensor nodes which provide a promising way forward to realize the vision of a trillion connected sensors in the next decade. However there are still many design challenges ahead to make these sensor nodes small,low-cost,secure,reliable and energy-efficient to name a few. Since the wireless nodes are expected to operate on a limited energy source or in some cases on harvested energy, the energy consumption of each building block is of prime importance to prolong the life of a sensor node. It has been found that the radio communication when active has been one of the highest power consuming modules on a sensor node. Low-energy protocols, e.g. processing the raw sensor data on-node, are more energy efficient for some applications as compared to transmitting the raw data over a wireless channel to a cloud server. In this thesis we explore signal processing techniques to realize a low power radio solution for wireless communication. Two prototype chips have been designed and their performance has been evaluated. The first prototype chip exploits compressed sensing for Ultra-Wide-Band (UWB) communication. UWB signals typically require a high ADC sampling rate in the receiver which results in high power consumption. Compressed sensing is demonstrated to relax the ADC sampling rate to save power. The second prototype chip exploits the sensitivity vs. power trade-off in a radio receiver to achieve iso-performance at lower power consumption and the time-varying wireless channel characteristics are used to adapt the sampling frequency of the receiver based on the SNR/Link quality of the communication channel, saving power, while maintaining the desired system performance. It is envisioned that embedded machine learning will play a key role in the integration of sensory data with prior knowledge for distributed intelligent sensing which might enable reduced wireless network traffic to a cloud server. A Near-Threshold hardware accelerator for arbitrary Bayesian network was designed for clique-tree message passing algorithm used for probabilistic inference. The hardware accelerator was benchmarked by the mid-size ALARM Bayesian network with total energy consumption of 76nJ for 250µS execution time.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/107130/1/oukhan_1.pd

Compact Digital Predistortion for Multi-band and Wide-band RF Transmitters

This thesis is focusing on developing a compact digital predistortion (DPD) system which costs less DPD added power consumptions. It explores a new theory and techniques to relieve the requirement of the number of training samples and the sampling-rate of feedback ADCs in DPD systems. A new theory about the information carried by training samples is introduced. It connects the generalized error of the DPD estimation algorithm with the statistical properties of modulated signals. Secondly, based on the proposed theory, this work introduces a compressed sample selection method to reduce the number of training samples by only selecting the minimal samples which satisfy the foreknown probability information. The number of training samples and complex multiplication operations required for coefficients estimation can be reduced by more than ten times without additional calculation resource. Thirdly, based on the proposed theory, this thesis proves that theoretically a DPD system using memory polynomial based behavioural modes and least-square (LS) based algorithms can be performed with any sampling-rate of feedback samples. The principle, implementation and practical concerns of the undersampling DPD which uses lower sampling-rate ADC are then introduced. Finally, the observation bandwidth of DPD systems can be extended by the proposed multi-rate track-and-hold circuits with the associated algorithm. By addressing several parameters of ADC and corresponding DPD algorithm, multi-GHz observation bandwidth using only a 61.44MHz ADC is achieved, and demonstrated the satisfactory linearization performance of multi-band and continued wideband RF transmitter applications via extensive experimental tests

Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

Exploring information retrieval using image sparse representations:from circuit designs and acquisition processes to specific reconstruction algorithms

New advances in the field of image sensors (especially in CMOS technology) tend to question the conventional methods used to acquire the image. Compressive Sensing (CS) plays a major role in this, especially to unclog the Analog to Digital Converters which are generally representing the bottleneck of this type of sensors. In addition, CS eliminates traditional compression processing stages that are performed by embedded digital signal processors dedicated to this purpose. The interest is twofold because it allows both to consistently reduce the amount of data to be converted but also to suppress digital processing performed out of the sensor chip. For the moment, regarding the use of CS in image sensors, the main route of exploration as well as the intended applications aims at reducing power consumption related to these components (i.e. ADC & DSP represent 99% of the total power consumption). More broadly, the paradigm of CS allows to question or at least to extend the Nyquist-Shannon sampling theory. This thesis shows developments in the field of image sensors demonstrating that is possible to consider alternative applications linked to CS. Indeed, advances are presented in the fields of hyperspectral imaging, super-resolution, high dynamic range, high speed and non-uniform sampling. In particular, three research axes have been deepened, aiming to design proper architectures and acquisition processes with their associated reconstruction techniques taking advantage of image sparse representations. How the on-chip implementation of Compressed Sensing can relax sensor constraints, improving the acquisition characteristics (speed, dynamic range, power consumption) ? How CS can be combined with simple analysis to provide useful image features for high level applications (adding semantic information) and improve the reconstructed image quality at a certain compression ratio ? Finally, how CS can improve physical limitations (i.e. spectral sensitivity and pixel pitch) of imaging systems without a major impact neither on the sensing strategy nor on the optical elements involved ? A CMOS image sensor has been developed and manufactured during this Ph.D. to validate concepts such as the High Dynamic Range - CS. A new design approach was employed resulting in innovative solutions for pixels addressing and conversion to perform specific acquisition in a compressed mode. On the other hand, the principle of adaptive CS combined with the non-uniform sampling has been developed. Possible implementations of this type of acquisition are proposed. Finally, preliminary works are exhibited on the use of Liquid Crystal Devices to allow hyperspectral imaging combined with spatial super-resolution. The conclusion of this study can be summarized as follows: CS must now be considered as a toolbox for defining more easily compromises between the different characteristics of the sensors: integration time, converters speed, dynamic range, resolution and digital processing resources. However, if CS relaxes some material constraints at the sensor level, it is possible that the collected data are difficult to interpret and process at the decoder side, involving massive computational resources compared to so-called conventional techniques. The application field is wide, implying that for a targeted application, an accurate characterization of the constraints concerning both the sensor (encoder), but also the decoder need to be defined