5 research outputs found
Analog Compressive Sensing for Multi-Channel Neural Recording: Modeling and Circuit Level Implementation
RÉSUMÉ
Dans cette thèse, nous présentons la conception d’un implant d’enregistrement neuronal multicanaux avec un échantillonnage compressé mis en oeuvre avec un procédé de fabrication CMOS à 65 nm.
La réduction de la technologie a˙ecte à la baisse les paramètres des amplificateurs neuronaux couplés en AC, comme la fréquence de coupure basse, en raison de l’e˙et de canal court des transistors MOS.
Nous analysons la fréquence de coupure basse et nous constatons que l’origine de ce problème, dans les technologies avancées, est la diminution de l’impédance d’entrée de l’amplificateur opérationnel de transconductance (OTA) en raison de la fuite d’oxyde de grille à l’entrée des OTA. Nous proposons deux solutions pour réduire la fréquence de coupure basse sans augmenter la valeur des condensateurs de rétroaction de l’étage d’entrée. La première solution est appelée rétroaction positive croisée et la deuxième solution utilise des PMOS à oxyde épais dans la paire de l’entrée di˙érentielle de l’OTA. Il est à noter que pour compresser le signal neuronal, nous utilisons le CS dans le domaine analogique.
Pour la réalisation, un intégrateur à capacité commutée est requis. Les paramètres non idéaux de l’OTA utilisé dans cet intégrateur, tels que le gain fini, la bande passante, la vitesse de balayage et le changement rapide de la sortie. Toutes ces imperfections induisent des erreurs et réduisent le rapport signal sur bruit (SNR) total. Nous avons simulé ces imperfections sur Matlab et Simulink pour définir les spécifications de l’OTA requis. Aussi, pour concevoir les circuits analogiques correspondant aux interfaces neuronales requises, tels qu’un amplificateur neuronal, une référence de tension compacte et à faible consommation d’énergie est requise. Nous avons proposé une référence de tension de faible consommation d’énergie sans utiliser le transistor bipolaire parasite de la technologie CMOS pour diminuer la surface de silicium requise. Finalement, nous avons complété l’encodeur de CS et un convertisseur analogique-numérique à approximation successive (SAR ADC) requis pour la chaine d’enregistrement des signaux neuronaux dans ce projet.----------ABSTRACT
In this thesis we present the design of a multi-channel neural recording implant with analog compressive sensing (CS) in 65 nm process.
Scaling down technology demotes the parameters of AC-coupled neural amplifiers, such as increasing the low-cuto˙ frequency due to the short-channel e˙ects of MOS transistors.
We analyze the low-cuto˙ frequency and find that the main reason of this problem in advanced technologies is decreasing the input resistance of the operational transconductance amplifier (OTA) due to the gate oxide static current leakage in the input of the OTA. In advanced technologies, the gate oxide is thin and some electrons can penetrate to the channel and cause DC current leakage. We proposed two solutions to reduce the low-cuto˙ frequency without increasing the value of the feedback capacitors of the front-end neural amplifier. The first solution is called cross-coupled positive feedback, and the second solution is utilizing thick-oxide PMOS transistors in the input di˙erential pair of the OTA. Compress the neural signal, we utilized the CS method in analog domain.
For its implementation, a switched-capacitor integrator is required. Non-ideal specifications of OTA of CS integrator such as finite gain, bandwidth, slew rate and output swing induce error and reduce the total signal to noise ratio (SNR). We simulated these non-idealities in Matlab and Simulink and extracted the specification of the required OTA. Also, to design analog circuits such as neural amplifier a low power and compact voltage reference is required. We implemented a low-power band-gap reference without utilizing parasitic bipolar transis-tor to decrease the silicon area. At the end, we completed the CS encoder and successive approximation architecture analog-to-digital converter (SAR ADC)
PROCESS AWARE ANALOG-CENTRIC SINGLE LEAD ECG ACQUISITION AND CLASSIFICATION CMOS FRONTEND
The primary objective of this research work is the development of a low power single-lead ECG
analog front-end (AFE) architecture which includes acquisition, digitization, process aware efficient
gain and frequency control mechanism and a low complexity classifier for the detecting asystole,
extreme bardycardia and tachycardia. Recent research on ECG recording systems focuses on the
design of a compact single-lead wearable/portable devices with ultra-low-power consumption and
in-built hardware for diagnosis and prognosis. Since, the amplitude of the ECG signal varies from
hundreds of µV to a few mV, and has a bandwidth of DC to 250 Hz, conventional front-ends use
an instrument amplifier followed by a programmable gain amplifier (PGA) to amplify the input
ECG signal appropriately. This work presents an mixed signal ECG fronted with an ultra-low
power two-stage capacitive-coupled signal conditioning circuit (or an AFE), providing programmable
amplification along with tunable 2nd order high pass and lowpass filter characteristics. In the
contemporary state-of-the-art ECG recording systems, the gain of the amplifier is controlled by
external digital control pins which are in turn dynamically controlled through a DSP. Therefore, an
efficient automatic gain control mechanism with minimal area overhead and consuming power in the
order of nano watts only. The AGC turns the subsequent ADC on only after output of the PGA (or
input of the ADC) reaches a level for which the ADC achieves maximum signal-to-noise-ratio (SNR),
hence saving considerable startup power and avoiding the use of DSP. Further, in any practical filter
design, the low pass cut-off frequency is prone to deviate from its nominal value across process
and temperature variations. Therefore, post-fabrication calibration is essential, before the signal
is fed to an ADC, to minimize this deviation, prevent signal degradation due to aliasing of higher
frequencies into the bandwidth
for classification of ECG signals, to switch to low resolution processing, hence saving power and
enhances battery lifetime. Another short-coming noticed in the literature published so far is that
the classification algorithm is implemented in digital domain, which turns out to be a power hungry
approach. Moreover, Although analog domain implementations of QRS complexes detection schemes
have been reported, they employ an external micro-controller to determine the threshold voltage. In
this regard, finally a power-efficient low complexity CMOS fully analog classifier architecture and a
heart rate estimator is added to the above scheme. It reduces the overall system power consumption
by reducing the computational burden on the DSP. The complete proposed scheme consists of (i)
an ultra-low power QRS complex detection circuit using an autonomous dynamic threshold voltage,
hence discarding the need of any external microcontroller/DSP and calibration (ii) a power efficient
analog classifier for the detection of three critical alarm types viz. asystole, extreme bradycardia
and tachycardia. Additionally, a heart rate estimator that provides the number of QRS complexes
within a period of one minute for cardiac rhythm (CR) and heart rate variability (HRV) analysis.
The complete proposed architecture is implemented in UMC 0.18 µm CMOS technology with 1.8 V
supply. The functionality of each of the individual blocks are successfully validated using postextraction
process corner simulations and through real ECG test signals taken from the PhysioNet
database. The capacitive feedback amplifier, Σ∆ ADC, AGC and the AFT are fabricated, and the
measurement results are discussed here. The analog classification scheme is successfully validated
using embed NXP LPC1768 board, discrete peak detector prototype and FPGA software interfac
Integrated circuit design for implantable neural interfaces
Progress in microfabrication technology has opened the way for new possibilities in
neuroscience and medicine. Chronic, biocompatible brain implants with recording and
stimulation capabilities provided by embedded electronics have been successfully demonstrated. However, more ambitious applications call for improvements in every aspect of
existing implementations. This thesis proposes two prototypes that advance the field in
significant ways. The first prototype is a neural recording front-end with spectral selectivity capabilities that implements a design strategy that leads to the lowest reported
power consumption as compared to the state of the art. The second one is a bidirectional front-end for closed-loop neuromodulation that accounts for self-interference and
impedance mismatch thus enabling simultaneous recording and stimulation. The design
process and experimental verification of both prototypes is presented herein
Low-Power Wireless Medical Systems and Circuits for Invasive and Non-Invasive Applications
Approximately 75% of the health care yearly budget of public health systems
around the world is spent on the treatment of patients with chronic diseases. This, along
with advances on the medical and technological fields has given rise to the use of
preventive medicine, resulting on a high demand of wireless medical systems (WMS) for
patient monitoring and drug safety research.
In this dissertation, the main design challenges and solutions for designing a
WMS are addressed from system-level, using off-the-shell components, to circuit
implementation. Two low-power oriented WMS aiming to monitor blood pressure of
small laboratory animals (implantable) and cardiac-activity (12-lead electrocardiogram)
of patients with chronic diseases (wearable) are presented. A power consumption vs.
lifetime analysis to estimate the monitoring unit lifetime for each application is included.
For the invasive/non-invasive WMS, in-vitro test benches are used to verify their
functionality showing successful communication up to 2.1 m/35 m with the monitoring
unit consuming 0.572 mA/33 mA from a 3 V/4.5 V power supply, allowing a two-year/
88-hour lifetime in periodic/continuous operation. This results in an improvement
of more than 50% compared with the lifetime commercial products.
Additionally, this dissertation proposes transistor-level implementations of an
ultra-low-noise/low-power biopotential amplifier and the baseband section of a wireless
receiver, consisting of a channel selection filter (CSF) and a variable gain amplifier
(VGA). The proposed biopotential amplifier is intended for electrocardiogram (ECG)/
electroencephalogram (EEG)/ electromyogram (EMG) monitoring applications and its architecture was designed focused on improving its noise/power efficiency. It was implemented using the ON-SEMI 0.5 µm standard process with an effective area of 360 µm2. Experimental results show a pass-band gain of 40.2 dB (240 mHz - 170 Hz), input referred noise of 0.47 Vrms, minimum CMRR of 84.3 dBm, NEF of 1.88 and a power dissipation of 3.5 µW. The CSF was implemented using an active-RC 4th order inverse-chebyshev topology. The VGA provides 30 gain steps and includes a DC-cancellation loop to avoid saturation on the sub-sequent analog-to-digital converter block. Measurement results show a power consumption of 18.75 mW, IIP3 of 27.1 dBm, channel rejection better than 50 dB, gain variation of 0-60dB, cut-off frequency tuning of 1.1-2.29 MHz and noise figure of 33.25 dB. The circuit was implemented in the standard IBM 0.18 µm CMOS process with a total area of 1.45 x 1.4 mm^(2).
The presented WMS can integrate the proposed biopotential amplifier and baseband section with small modifications depending on the target signal while using the low-power-oriented algorithm to obtain further power optimization