A Polynomial Description of the Rijndael Advanced Encryption Standard

The paper gives a polynomial description of the Rijndael Advanced Encryption Standard recently adopted by the National Institute of Standards and Technology. Special attention is given to the structure of the S-Box.Comment: 12 pages, LaTe

Algebraic Construction and Cryptographic Properties of Rijndael Substitution Box

Rijndael algorithm was selected as the advanced encryption standard in 2001 after five year long security evaluation; it is well proven in terms of its strength and efficiency. The substitution box is the back bone of the cipher and its strength lies in the simplicity of its algebraic construction. The present paper is a study of the construction of Rijndael Substitution box and the effect of varying the design components on its cryptographic properties.Defence Science Journal, 2012, 62(1), pp.32-37, DOI:http://dx.doi.org/10.14429/dsj.62.143

A fully pipelined memoryless 17.8 Gbps AES-128 encryptor

A fully pipelined implementation of the Advanced Encryption Stan-dard encryption algorithm with 128-bit input and key length (AES-128) was implemented on Xilinx ’ Virtex-E and Virtex-II devices. The design is called SIG-AES-E and it implements the S-boxes combinatorially and thus requires no internal memory. It is con-cluded, that SIG-AES-E is faster than other published FPGA-based implementations of the AES-128 encryption algorithm. Categories and Subject Descriptor

Implementation and Optimization of the Advanced Encryption Standard Algorithm on an 8-Bit Field Programmable Gate Array Hardware Platform

The contribution of this research is three-fold. The first is a method of converting the area occupied by a circuit implemented on a Field Programmable Gate Array (FPGA) to an equivalent as a measure of total gate count. This allows direct comparison between two FPGA implementations independent of the manufacturer or chip family. The second contribution improves the performance of the Advanced Encryption Standard (AES) on an 8-bit computing platform. This research develops an AES design that occupies less than three quarters of the area reported by the smallest design in current literature as well as significantly increases area efficiency. The third contribution of this research is an examination of how various designs for the critical AES SubBytes and MixColumns transformations interact and affect the overall performance of AES. The transformations responsible for the largest variance in performance are identified and the effect is measured in terms of throughput, area efficiency, and area occupied

Design and implementation of Area optimized 256 bit Advanced encryption standard on FPGA

This paper presents architecture of the Advanced Encryption Standard (AES-Rijndael) cryptosystem. The reconfigurable architecture is capable of handling all possible combinations of standard bit lengths (128,192,256) of data and key. The two main parts of AES algorithm, namely encryption and key expansion, are considered for optimization. The major optimization criteria considered are maximization of hardware reduction and path delay reduction. The fully rolled inner-pipelined architecture ensures lesser hardware complexity. A new AES algorithm with 256-bit keys (AES-256) was described in this paper, which is to be realized in Verilog Hardware Description Language on FPGA board. In this novel work, substantial improvement in performance in terms of area, power and dynamic speed will obtained. This will give low complexity architecture and will easily achieve low latency as well as high throughput. DOI: 10.17762/ijritcc2321-8169.15027

Rijndael Circuit Level Cryptanalysis

The Rijndael cipher was chosen as the Advanced Encryption Standard (AES) in August 1999. Its internal structure exhibits unusual properties such as a clean and simple algebraic description for the S-box. In this research, we construct a scalable family of ciphers which behave very much like the original Rijndael. This approach gives us the opportunity to use computational complexity theory. In the main result, we generate a candidate one-way function family from the scalable Rijndael family. We note that, although reduction to one-way functions is a common theme in the theory of public-key cryptography, it is rare to have such a defense of security in the private-key theatre. In this thesis a plan of attack is introduced at the circuit level whose aim is not break the cryptosystem in any practical way, but simply to break the very bold Rijndael security claim. To achieve this goal, we are led to a formal understanding of the Rijndael security claim, juxtaposing it with rigorous security treatments. Several of the questions that arise in this regard are as follows: ``Do invertible functions represented by circuits with very small numbers of gates have better than worst case implementations for their inverses?\u27 ``How many plaintext/ciphertext pairs are needed to uniquely determine the Rijndael key?\u2

FPGA Implementation of Advanced Encryption Standard

Security is a crucial parameter to be recognized with the improvement of electronic communication. Today most research in the field of electronic communication includes look into on security concern of communication. At present most by and large consumed and recognized standard for encryption of data is the Advanced Encryption Standard. AES was transformed to supplant the developing Data Encryption Standard. The AES calculation is fit for handling cryptographic keys which are of 256, 128, & 192 bits to encode & unscramble data in squares of 128 bits. The center of the calculation is made up of four key parts, which manage 8 bit data pieces. The whole 128 bit data to the calculation is dealt with into a 4 x 4 grid termed a state, to obtain the 8 bit square. Considering the complex nature of advance encryption standard (AES) algorithm, it requires a huge amount of hardware resources for its practical implementation. The extreme amount of hardware requirement makes its hardware implementation very burdensome. During this research, a FPGA scheme is introduced which is highly efficient in terms of resource utilization. In this scheme implementation of AES algorithm is done as a finite state machine (FSM). VHDL is used as a programming language for the purpose of design. Data path and control unit are designed for both cipher and decipher block, after that respective data path and control unit are integrated using structural modeling style of VHDL. Xilinx_ISE_14.2 software is being used for the purpose of simulating and optimizing the synthesizable VHDL code. The working of the implemented algorithm is tested using VHDL test bench wave form of Xilinx ISE simulator and resource utilization is also presented for a targeted Spartan3e XC3s500e FPGA

Efficient software implementation of AES on 32-bit platforms

Rijndael is the winner algorithm of the AES contest; therefore it should become the most used symmetric-key cryptographic algorithm. One important application of this new standard is cryptography on smart cards. In this paper we present an optimisation of the Rijndael algorithm to speed up execution on 32-bits processors with memory constraints, such as those used in smart cards. First a theoretical analysis of the Rijndael algorithm and of the proposed optimisation is discussed, and then simulation results of the optimised algorithm on different processors are presented and compared with other reference implementations, as known from the technical literature