Platform-based design, test and fast verification flow for mixed-signal systems on chip

This research is providing methodologies to enhance the design phase from architectural space exploration and system study to verification of the whole mixed-signal system. At the beginning of the work, some innovative digital IPs have been designed to develop efficient signal conditioning for sensor systems on-chip that has been included in commercial products. After this phase, the main focus has been addressed to the creation of a re-usable and versatile test of the device after the tape-out which is close to become one of the major cost factor for ICs companies, strongly linking it to model’s test-benches to avoid re-design phases and multi-environment scenarios, producing a very effective approach to a single, fast and reliable multi-level verification environment. All these works generated different publications in scientific literature. The compound scenario concerning the development of sensor systems is presented in Chapter 1, together with an overview of the related market with a particular focus on the latest MEMS and MOEMS technology devices, and their applications in various segments. Chapter 2 introduces the state of the art for sensor interfaces: the generic sensor interface concept (based on sharing the same electronics among similar applications achieving cost saving at the expense of area and performance loss) versus the Platform Based Design methodology, which overcomes the drawbacks of the classic solution by keeping the generality at the highest design layers and customizing the platform for a target sensor achieving optimized performances. An evolution of Platform Based Design achieved by implementation into silicon of the ISIF (Intelligent Sensor InterFace) platform is therefore presented. ISIF is a highly configurable mixed-signal chip which allows designers to perform an effective design space exploration and to evaluate directly on silicon the system performances avoiding the critical and time consuming analysis required by standard platform based approach. In chapter 3 we describe the design of a smart sensor interface for conditioning next generation MOEMS. The adoption of a new, high performance and high integrated technology allow us to integrate not only a versatile platform but also a powerful ARM processor and various IPs providing the possibility to use the platform not only as a conditioning platform but also as a processing unit for the application. In this chapter a description of the various blocks is given, with a particular emphasis on the IP developed in order to grant the highest grade of flexibility with the minimum area occupation. The architectural space evaluation and the application prototyping with ISIF has enabled an effective, rapid and low risk development of a new high performance platform achieving a flexible sensor system for MEMS and MOEMS monitoring and conditioning. The platform has been design to cover very challenging test-benches, like a laser-based projector device. In this way the platform will not only be able to effectively handle the sensor but also all the system that can be built around it, reducing the needed for further electronics and resulting in an efficient test bench for the algorithm developed to drive the system. The high costs in ASIC development are mainly related to re-design phases because of missing complete top-level tests. Analog and digital parts design flows are separately verified. Starting from these considerations, in the last chapter a complete test environment for complex mixed-signal chips is presented. A semi-automatic VHDL-AMS flow to provide totally matching top-level is described and then, an evolution for fast self-checking test development for both model and real chip verification is proposed. By the introduction of a Python interface, the designer can easily perform interactive tests to cover all the features verification (e.g. calibration and trimming) into the design phase and check them all with the same environment on the real chip after the tape-out. This strategy has been tested on a consumer 3D-gyro for consumer application, in collaboration with SensorDynamics AG

DESIGN AND VALIDATION OF ELECTRONIC SYSTEMS FOR SENSOR CONDITIONING

In the last few years the great advances in process technology has lead to a dramatic increase of the density of electronic functions, furthermore latest refinements in photolithography techniques has featured an increasing shrinking of dimension of sensing elements up to the development of the Micro Electro Mechanical Systems (MEMS) in which mechanical elements, sensors, actuators, and electronics are integrated on a common silicon substrate. This rapid development of integrated systems has had a strong impact on a wide range of applications whose field of interest is focussed on sensing, conditioning and actuating activity. If in the last decades the diffusion of measurement systems was limited by high costs, large size and low reliability, the new generations of MEMS sensors guarantee remarkable savings in cost, area and power consumption featuring a deep spreading of the possible application for such systems in various market fields. This thesis deals with the development of sensor systems mainly targeting the new generation of MEMS sensors, which achieves a great reduction of area and power consumption but on the other hand requires more complexity in the conditioning interface. This work also faces the emerging issues deriving by the increasing complexity of electronic interface tight with the constant reduction of time to market which forces companies to review the design flow to maintain a high level of product quality. This research is then providing new tools and methodologies to enhance the design phase from architectural space exploration to verification of the whole system, and joining pre-silicon simulations to post-silicon verification aiding testing of electronic systems which is close to become one of the major cost factor for ICs companies. The compound scenario concerning the development of sensor systems is presented in Chapter 1, together with an overview of sensor systems market with a particular focus on the latest MEMS technology devices, and related applications in various segments. Chapter 2 introduces the state of the art for sensor interfaces: the generic sensor interface concept (based on sharing the same electronics among similar applications achieving cost saving at the expense of area and performance loss); and the Platform Based Design methodology which overcomes the drawbacks of generic sensor interfaces by keeping the generality at the highest design layers and customizing the platform for a target sensor achieving optimized performances. An evolution of Platform Based Design achieved by implementation into silicon of the ISIF (Intelligent Sensor InterFace) platform is therefore presented. ISIF is a highly configurable mixed-signal chip which allows designers to perform an effective design space exploration and to evaluate directly on silicon the system performances avoiding the critical and time consuming analysis required by standard platform based approach. Chapter 3 describes a verification and validation methodology for complex mixed signal ICs. A VHDL-AMS system verification methodology allows designers to derive VHDL-AMS models from full-custom schematics through a semi-automatic approach (featuring modeling time reduction and coherency between models and schematics), obtaining a behavioral model of the whole analog section for top level system verifications. The verification environment has been also enhanced by an integrated flow to bridge pre-silicon simulation to post-silicon verification relieving time consuming procedures for testing the prototype and featuring automatic data exchange between design and test environments. In Chapter 4 an application of the ISIF platform for design and validation of a sensor system for measuring water flow based on a hot wire anemometer in MEMS technology is described. The ISIF approach and the tools developed in the proposed verification flow have featured a fast and accurate evaluation of the whole sensor system overcoming time consuming system simulations needed in traditional approaches for architectural exploration and bringing to light phenomena related to the sensor and the surrounding media of the tailored application hardly foreseeable at system level. In the last chapter we describe the design of a smart sensor interface for conditioning all resistive class of sensor to face the market demand for low cost, optimized, high performance sensor systems. The proposed interface combines high quality signal conditioning with low size and advanced low power techniques, embodying an optimal candidate for mass production. The architectural space evaluation and the application prototyping with ISIF has enabled an effective, rapid and low risk development of the interface achieving an optimized sensor system for water flow monitoring achieving the high performances obtained with ISIF with noteworthy savings on area, cost and powe

An Adaptive Design Methodology for Reduction of Product Development Risk

Embedded systems interaction with environment inherently complicates understanding of requirements and their correct implementation. However, product uncertainty is highest during early stages of development. Design verification is an essential step in the development of any system, especially for Embedded System. This paper introduces a novel adaptive design methodology, which incorporates step-wise prototyping and verification. With each adaptive step product-realization level is enhanced while decreasing the level of product uncertainty, thereby reducing the overall costs. The back-bone of this frame-work is the development of Domain Specific Operational (DOP) Model and the associated Verification Instrumentation for Test and Evaluation, developed based on the DOP model. Together they generate functionally valid test-sequence for carrying out prototype evaluation. With the help of a case study 'Multimode Detection Subsystem' the application of this method is sketched. The design methodologies can be compared by defining and computing a generic performance criterion like Average design-cycle Risk. For the case study, by computing Average design-cycle Risk, it is shown that the adaptive method reduces the product development risk for a small increase in the total design cycle time.Comment: 21 pages, 9 figure

A software definable MIMO testbed: architecture and functionality

Following the intensive theoretical studies of recently emerged MIMO technology, a variety of performance measures become important to investigate the challenges and trade-offs at various levels throughout MIMO system design process. This paper presents a review of the MIMO testbed recently set up at King’s College London. The architecture that distinguishes the testbed as a flexible and reconfigurable system is first preseneted. This includes both the hardware and software aspects, and is followed by a discussion of implementation methods and evaluation of system research capabilities

MISMATCH: A basis for semi-automatic functional mixed-signal test-pattern generation

This paper describes a tool which assists the designer in the rapid generation of functional tests for mixed-signal circuits down to the actual test-signals for the tester. The tool is based on manipulating design data, making use of macro-based test libraries and tester resources provided by the test engineer, and computer-based interaction with the designe

Time-efficient fault detection and diagnosis system for analog circuits

Time-efficient fault analysis and diagnosis of analog circuits are the most important prerequisites to achieve online health monitoring of electronic equipments, which are involving continuing challenges of ultra-large-scale integration, component tolerance, limited test points but multiple faults. This work reports an FPGA (field programmable gate array)-based analog fault diagnostic system by applying two-dimensional information fusion, two-port network analysis and interval math theory. The proposed system has three advantages over traditional ones. First, it possesses high processing speed and smart circuit size as the embedded algorithms execute parallel on FPGA. Second, the hardware structure has a good compatibility with other diagnostic algorithms. Third, the equipped Ethernet interface enhances its flexibility for remote monitoring and controlling. The experimental results obtained from two realistic example circuits indicate that the proposed methodology had yielded competitive performance in both diagnosis accuracy and time-effectiveness, with about 96% accuracy while within 60 ms computational time.Peer reviewedFinal Published versio