2,086 research outputs found

    Structured, technology independent VLSI design

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    Journal ArticleRapid advancement in new semiconductor technologies has created a need for the design of existing integrated circuits using these new technologies. These new technologies are required to provide improved performance, smaller feature sizes and lower costs. The conversion of an integrated circuit from an existing technology to a new technology, however, is very difficulty with existing CAD tools. In this research, we have concentrated on developing a structured, technology independent VLSI design methodology, with the goal of theoretically quantifying technology independence and systematically performing technology transformation. We have identified the nature of the problems, using techniques developed during our past research, within the context of particular semiconductor technologies such as CMOS and GaAs technologies

    Automatic synthesis of reconfigurable instruction set accelerators

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    VLSI design methodology

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    Parameter Synthesis in Markov Models: A Gentle Survey

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    This paper surveys the analysis of parametric Markov models whose transitions are labelled with functions over a finite set of parameters. These models are symbolic representations of uncountable many concrete probabilistic models, each obtained by instantiating the parameters. We consider various analysis problems for a given logical specification φ\varphi: do all parameter instantiations within a given region of parameter values satisfy φ\varphi?, which instantiations satisfy φ\varphi and which ones do not?, and how can all such instantiations be characterised, either exactly or approximately? We address theoretical complexity results and describe the main ideas underlying state-of-the-art algorithms that established an impressive leap over the last decade enabling the fully automated analysis of models with millions of states and thousands of parameters

    Fast structured design of VLSI circuits

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    technical reportWe believe that a structured, user-friendly, cost-effective tool for rapid implementation of VLSI circuits which encourages students to participate directly in research projects are the key components in digital integrated circuit (IC) education. In this paper, we introduce our VLSI education activities, with t h e emphasis on t h e presentation of Path Programmable Logic (PPL) design methodology, in addition to a short description of a representative student project. Students using PPL are able to implement MOS or GaAs VLSI circuits with several thousands to over 100,000 transistors in a few weeks. They have designed and built numerous VLSI architectures and computer systems which play an influential role in various research areas. Our educational activities and the Utah Annual Student VLSI Design Contest supported by over a dozen leading American firms have attracted multiple university involvement in recent years

    Flame Retardants

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    Flame retardants reduce the risk of fire by decreasing the combustion rate and flame propagation in the presence of fire, leading to the prevention and control of fire. Flame Retardants is divided into four sections: section 1 consists of the introduction, section 2 discusses properties, Section 3 comprises nanocomposites, and section 4 includes computational analysis. The book will be useful for scientists and researchers interested in the field of fire control

    Parameter Synthesis for Markov Models

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    Markov chain analysis is a key technique in reliability engineering. A practical obstacle is that all probabilities in Markov models need to be known. However, system quantities such as failure rates or packet loss ratios, etc. are often not---or only partially---known. This motivates considering parametric models with transitions labeled with functions over parameters. Whereas traditional Markov chain analysis evaluates a reliability metric for a single, fixed set of probabilities, analysing parametric Markov models focuses on synthesising parameter values that establish a given reliability or performance specification φ\varphi. Examples are: what component failure rates ensure the probability of a system breakdown to be below 0.00000001?, or which failure rates maximise reliability? This paper presents various analysis algorithms for parametric Markov chains and Markov decision processes. We focus on three problems: (a) do all parameter values within a given region satisfy φ\varphi?, (b) which regions satisfy φ\varphi and which ones do not?, and (c) an approximate version of (b) focusing on covering a large fraction of all possible parameter values. We give a detailed account of the various algorithms, present a software tool realising these techniques, and report on an extensive experimental evaluation on benchmarks that span a wide range of applications.Comment: 38 page

    The 1991 3rd NASA Symposium on VLSI Design

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    Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

    A finite state machine synthesizer

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    This thesis presents a Finite State Machine (FSM) Synthesizer developed at Portland State University. The synthesizer starts from a high level behavioral description, in which no states are specified, and generates the lower level FSM descriptions for simulation and physical layout generation

    Using Fine Grain Approaches for highly reliable Design of FPGA-based Systems in Space

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    Nowadays using SRAM based FPGAs in space missions is increasingly considered due to their flexibility and reprogrammability. A challenge is the devices sensitivity to radiation effects that increased with modern architectures due to smaller CMOS structures. This work proposes fault tolerance methodologies, that are based on a fine grain view to modern reconfigurable architectures. The focus is on SEU mitigation challenges in SRAM based FPGAs which can result in crucial situations
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