Parallelization of Stochastic Evolution for Cell Placement

VLSI physical design and the problems related to it such as placement, channel routing, etc, carry inherent complexities that are best dealt with iterative heuristics. However the major drawback of these iterative heuristics has been the large runtime involved in reaching acceptable solutions especially when optimizing for multiple objectives. Among the acceleration techniques proposed, parallelization is one promising method. Distributed memory multiprocessor systems and shared memory multiprocessor systems have gained considerable attention in recent years of research. This idea of parallel computing has attracted both the researchers and manufacturers who are targeting to reduce the time to market. Our objective is to exploit the benefits of parallel computing for a time consuming placement problem in VLSI. Finding the best solution for the placement of n modules is a hard problem. Thus the enumerative search techniques, specially those which employ the brute force, are unaccepted for the circuits in which n (number of modules) is large. Constructive and Iterative heuristics play the key role in this scenario and hence are frequently used. We will use Stochastic Evolution for finding the optimal solution to the above mentioned placement problem where the major task in our objective will be the parallelization of Stochastic Evolution using different parallelization techniques and the comparison between these different parallelized versions based on the results achieved. The parallelization will be carried out using MPI (Message Passing Interface) on a distributed memory multiprocessor system and conclusion will be based on the results achieved that are expected to show speedup nearly equal to linear speedup when run over increasing number of processors

A Parallel Tabu Search Algorithm for Optimizing Multiobjective VLSI Placement

Abstract. In this paper, we present a parallel tabu search (TS) algorithm for efficient optimization of a constrained multiobjective VLSI standard cell placement problem. The primary purpose is to accelerate TS algorithm to reach near optimal placement solutions for large circuits. The proposed technique employs a candidate list partitioning strategy based on distribution of mutually disjoint set of moves among the slave processes. The implementation is carried out on a dedicated cluster of workstations. Experimental results using ISCAS-85/89 benchmark circuits illustrating quality and speedup trends are presented. A comparison of the obtained results is made with the results of a parallel genetic algorithm (GA) implementation

A Parallel Tabu Search Algorithm for Optimizing Multiobjective VLSI Placement

Abstract. In this paper, we present a parallel tabu search (TS) algorithm for efficient optimization of a constrained multiobjective VLSI standard cell placement problem. The primary purpose is to accelerate TS algorithm to reach near optimal placement solutions for large circuits. The proposed technique employs a candidate list partitioning strategy based on distribution of mutually disjoint set of moves among the slave processes. The implementation is carried out on a dedicated cluster of workstations. Experimental results using ISCAS-85/89 benchmark circuits illustrating quality and speedup trends are presented. A comparison of the obtained results is made with the results of a parallel genetic algorithm (GA) implementation

Parallelization of Stochastic Evolution for Cell Placement

VLSI physical design and the problems related to it such as placement, channel routing, etc, carry inherent complexities that are best dealt with iterative heuristics. However the major drawback of these iterative heuristics has been the large runtime involved in reaching acceptable solutions especially when optimizing for multiple objectives. Among the acceleration techniques proposed, parallelization is one promising method. Distributed memory multiprocessor systems and shared memory multiprocessor systems have gained considerable attention in recent years of research. This idea of parallel computing has attracted both the researchers and manufacturers who are targeting to reduce the time to market. Our objective is to exploit the benefits of parallel computing for a time consuming placement problem in VLSI. Finding the best solution for the placement of n modules is a hard problem. Thus the enumerative search techniques, specially those which employ the brute force, are unaccepted for the circuits in which n (number of modules) is large. Constructive and Iterative heuristics play the key role in this scenario and hence are frequently used. We will use Stochastic Evolution for finding the optimal solution to the above mentioned placement problem where the major task in our objective will be the parallelization of Stochastic Evolution using different parallelization techniques and the comparison between these different parallelized versions based on the results achieved. The parallelization will be carried out using MPI (Message Passing Interface) on a distributed memory multiprocessor system and conclusion will be based on the results achieved that are expected to show speedup nearly equal to linear speedup when run over increasing number of processors

Parallelization of Stochastic Evolution for Cell Placement

VLSI physical design and the problems related to it such as placement, channel routing, etc, carry inherent complexities that are best dealt with iterative heuristics. However the major drawback of these iterative heuristics has been the large runtime involved in reaching acceptable solutions especially when optimizing for multiple objectives. Among the acceleration techniques proposed, parallelization is one promising method. Distributed memory multiprocessor systems and shared memory multiprocessor systems have gained considerable attention in recent years of research. This idea of parallel computing has attracted both the researchers and manufacturers who are targeting to reduce the time to market. Our objective is to exploit the benefits of parallel computing for a time consuming placement problem in VLSI. Finding the best solution for the placement of n modules is a hard problem. Thus the enumerative search techniques, specially those which employ the brute force, are unaccepted for the circuits in which n (number of modules) is large. Constructive and Iterative heuristics play the key role in this scenario and hence are frequently used. We will use Stochastic Evolution for finding the optimal solution to the above mentioned placement problem where the major task in our objective will be the parallelization of Stochastic Evolution using different parallelization techniques and the comparison between these different parallelized versions based on the results achieved. The parallelization will be carried out using MPI (Message Passing Interface) on a distributed memory multiprocessor system and conclusion will be based on the results achieved that are expected to show speedup nearly equal to linear speedup when run over increasing number of processors

Using ant colony optimization for routing in microprocesors

Power consumption is an important constraint on VLSI systems. With the advancement in technology, it is now possible to pack a large range of functionalities into VLSI devices. Hence it is important to find out ways to utilize these functionalities with optimized power consumption. This work focuses on curbing power consumption at the design stage. This work emphasizes minimizing active power consumption by minimizing the load capacitance of the chip. Capacitance of wires and vias can be minimized using Ant Colony Optimization (ACO) algorithms. ACO provides a multi agent framework for combinatorial optimization problems and hence is used to handle multiple constraints of minimizing wire-length and vias to achieve the goal of minimizing capacitance and hence power consumption. The ACO developed here is able to achieve an 8% reduction of wire-length and 7% reduction in vias thereby providing a 7% reduction in total capacitance, compared to other state of the art routers

Fuzzy simulated evolution algorithm for VLSI cell placement

Placement is a major step encountered during the design of very large scale integrated circuits. It is a generalization of the quadratic assignment problem with numerous constraints, several objectives, and a very noisy solution space. Besides the NP-hard nature of this problem, many circuit parameters such as area, interconnect delays, wire requirements, etc. can only be imprecisely estimated before completing the remaining design automation steps and committing the circuit to silicon. Further, the best placement is usually one that combines several desirable physical characteristics. There has not been a consensus on how to accommodate all these (conflicting) requirements in the search for near optimal feasible solutions. In this paper, we present a fuzzy simulated evolution (FSE) algorithm to tackle this problem. Identification of near optimal solutions is achieved through a novel goal-directed fuzzy search approach. This approach can be followed by other iterative (meta-) heuristics to find desirable solutions to optimization problems with noisy search space and possibly more than one objective. This approach is dominance preserving, i.e. if a solution A dominates another solution B with respect to all objective criteria, then A will surely have a higher membership in the fuzzy set of good solutions than solution B. Further, the approach scales well with larger problem instances and/or a larger number of objective criteria. Also, the operators of all stages of simulated evolution have been implemented using fuzzy logic to exploit the nature of fuzzy information of the problem domain. Experiments with benchmark tests demonstrate a noticeable improvement in solution quality. (C) 2002 Published by Elsevier Science Ltd

Simulated evolution for timing and low power VLSI standard cell placement

Abstract This paper presents a Fuzzy Simulated Evolution algorithm for VLSI standard cell placement with the objective of minimizing power, delay and area. For this hard multiobjective combinatorial optimization problem, no known exact and efficient algorithms exist that guarantee finding a solution of specific or desirable quality. Approximation iterative heuristics such as Simulated Evolution are best suited to perform an intelligent search of the solution space. Due to the imprecise nature of design information at the placement stage the various objectives and constraints are expressed in the fuzzy domain. The search is made to evolve toward a vector of fuzzy goals. Variants of the algorithm which include adaptive bias and biasless simulated evolution are proposed and experimental results are presented. Comparison with genetic algorithm is discussed. r 2003 Elsevier Ltd. All rights reserved

Simulated evolution for timing and low power VLSI standard cell placement

Abstract This paper presents a Fuzzy Simulated Evolution algorithm for VLSI standard cell placement with the objective of minimizing power, delay and area. For this hard multiobjective combinatorial optimization problem, no known exact and efficient algorithms exist that guarantee finding a solution of specific or desirable quality. Approximation iterative heuristics such as Simulated Evolution are best suited to perform an intelligent search of the solution space. Due to the imprecise nature of design information at the placement stage the various objectives and constraints are expressed in the fuzzy domain. The search is made to evolve toward a vector of fuzzy goals. Variants of the algorithm which include adaptive bias and biasless simulated evolution are proposed and experimental results are presented. Comparison with genetic algorithm is discussed. r 2003 Elsevier Ltd. All rights reserved