Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures

In this paper, a method is proposed for extraction of coupled networks from layout information for simulation of electrothermal device behavior. The networks represent a three-dimensional (3-D) device structure with circuit elements. The electrical and thermal characteristics of this circuit representation are calculated with a circuit simulator. Spatial potential distributions, current flows, and temperature distributions in the device structure are calculated on the spatial coordinates. This simulation method can be placed between device simulation and (conventional) circuit simulation. It has been implemented in a circuit simulator and is demonstrated for simulation of self-heating in a bipolar low frequency power transistor. The main advantage of this simulation method is that not only the 3-D thermal behavior of the whole chip is simulated, but that this is also directly coupled to the electrical device behavior by means of the power dissipation and temperature distribution in the device. This offers the possibility for the circuit designer to simulate 3-D, coupled, thermal-electrical problems with a circuit simulator. As an example, the influence of the emitter contacting on the internal temperature and current distribution of a BJT is investigate

Evaluation of a gate capacitance in the sub-aF range for a chemical field-effect transistor with a silicon nanowire channel

An evaluation of the gate capacitance of a field-effect transitor (FET) whose channel length and width are several ten nanometer, is a key point for sensors applications. However, experimental and precise evaluation of capacitance in the aF range or less has been extremely difficult. Here, we report an extraction of the capacitance down to 0.55 aF for a silicon FET with a nanoscale wire channel whose width and length are 15 and 50 nm, respectively. The extraction can be achieved by using a combination of four kinds of measurements: current characteristics modulated by double gates, random-telegraph-signal noise induced by trapping and detrapping of a single electron, dielectric polarization noise, and current characteristics showing Coulomb blockade at low temperature. The extraction of such a small gate capacitance enables us to evaluate electron mobility in a nanoscale wire using a classical model of current characteristics of a FET.Comment: To be published in IEEE Trans. Nanotechno

An Algorithmic Framework for Efficient Large-Scale Circuit Simulation Using Exponential Integrators

We propose an efficient algorithmic framework for time domain circuit simulation using exponential integrator. This work addresses several critical issues exposed by previous matrix exponential based circuit simulation research, and makes it capable of simulating stiff nonlinear circuit system at a large scale. In this framework, the system's nonlinearity is treated with exponential Rosenbrock-Euler formulation. The matrix exponential and vector product is computed using invert Krylov subspace method. Our proposed method has several distinguished advantages over conventional formulations (e.g., the well-known backward Euler with Newton-Raphson method). The matrix factorization is performed only for the conductance/resistance matrix G, without being performed for the combinations of the capacitance/inductance matrix C and matrix G, which are used in traditional implicit formulations. Furthermore, due to the explicit nature of our formulation, we do not need to repeat LU decompositions when adjusting the length of time steps for error controls. Our algorithm is better suited to solving tightly coupled post-layout circuits in the pursuit for full-chip simulation. Our experimental results validate the advantages of our framework.Comment: 6 pages; ACM/IEEE DAC 201

Present status of development of damping ring extraction kicker system for CLIC

The CLIC damping rings will produce ultra-low emittance beam, with high bunch charge, necessary for the luminosity performance of the collider. To limit the beam emittance blow-up due to oscillations, the pulse power modulators for the damping ring kickers must provide extremely flat, high-voltage pulses: specifications call for a 160 ns duration and a flattop of 12.5 kV, 250 A, with a combined ripple and droop of not more than \pm0.02 %. The stripline design is also extremely challenging: the field for the damping ring kicker system must be homogenous to within \pm0.01 % over a 1 mm radius, and low beam coupling impedance is required. The solid-state modulator, the inductive adder, is a very promising approach to meeting the demanding specifications for the field pulse ripple and droop. This paper describes the initial design of the inductive adder and the striplines of the kicker system.Comment: Proceedings of LCWS'11, International Workshop on Future Linear Colliders, Granada, Spain 26-30 Sept 201

Graphene field-effect transistors based on boron nitride gate dielectrics

Graphene field-effect transistors are fabricated utilizing single-crystal hexagonal boron nitride (h-BN), an insulating isomorph of graphene, as the gate dielectric. The devices exhibit mobility values exceeding 10,000 cm2/V-sec and current saturation down to 500 nm channel lengths with intrinsic transconductance values above 400 mS/mm. The work demonstrates the favorable properties of using h-BN as a gate dielectric for graphene FETs.Comment: 4 pages, 8 figure