Design and analysis of a low-profile two-axis solar tracker with hybridized control

The adoption of solar power technologies throughout the world is increasing rapidly. Solar trackers are a necessary component in Concentrated Solar Power (CSP) applications and have also shown up to 46% per annum energy increase in photovoltaic (PV) panels when compared with fixed mounted panels. To resist wind forces, trackers typically incorporate heavy structural components and reinforced concrete foundations. Thus, the manufacture and installation of trackers is costly due to their size, weight, and careful consideration of geological conditions. This work presents a new solar tracker design for use with concentrating solar power and photovoltaic panels. The tracker is comprised of two coplanar perpendicular linear actuators and one linkage arm that can track the sun in two axes. A hybrid control strategy combines time and location based solar position estimates, with a two-axis misalignment sensor for a robust control strategy. Part cost is lowered by the low profile tracker geometry by allowing lighter structural and actuation components to combat gusty conditions, and installation costs are reduced by the wide footprint of the system, mitigating the need for deep foundations. A tracker prototype is built and tested for functionality and tracking accuracy. Testing shows an average mechanical pointing hysteresis of 0.05 [degrees]. The tracker is outfitted with a parabolic mirror and blackbody receiving cavity, and in full sun reaches a steady-state temperature of 670 [degrees] C

Development of microsystems for point-of-use microorganism detection

2018 Summer.Includes bibliographical references.To view the abstract, please see the full text of the document

Crexens™: an expandable general-purpose electrochemical analyzer

2019 Fall.Includes bibliographical references.Electrochemical analysis has gained a great deal of attention of late due to its low-cost, easy-to-perform, and easy-to-miniaturize, especially in personal health care where accuracy and mobility are key factors to bring diagnostics to patients. According to data from Centers for Medicare & Medicaid Services (CMS) in the US, the share of health expenditure in the US has been kept growing in the past 3 decades and reached 17.9% of its overall Gross Domestic Product till 2016, which is equivalent to $10,348 for every person in the US per year. On the other hand, health care resources are often limited not only in rural area but also appeared in well-developed countries. The urgent need and the lack of health resource brings to front the research interest of Point-of-Care (PoC) diagnosis devices. Electrochemical methods have been largely adopted by chemist and biologist for their research purposes. However, several issues exist within current commercial benchtop instruments for electrochemical measurement. First of all, the current commercial instruments are usually bulky and do not have handheld feature for point-of-care applications and the cost are easily near$5,000 each or above. Secondly, most of the instruments do not have good integration level that can perform different types of electrochemical measurements for different applications. The last but not the least, the existing generic benchtops instruments for electrochemical measurements have complex operational procedures that require users to have a sufficient biochemistry and electrochemistry background to operate them correctly. The proposed Crexens™ analyzer platform is aimed to present an affordable electrochemical analyzerwhile achieving comparable performance to the existing commercial instruments, thus, making general electrochemical measurement applications accessible to general public. In this dissertation, the overall Crexens™ electrochemical analyzer architecture and its evolution are presented. The foundation of the Crexens™ architecture was derived from two separate but related research in electrochemical sensing. One of them is a microelectrode sensor array using CMOS for neurotransmitter sensing; the other one is a DNA affinity-based capacitive sensor for infectious disease, such as ZIKA. The CMOS microelectrode sensor array achieved a 320uM sensitivity for norepinephrine, whereas the capacitive sensor achieved a dynamic range of detection from 1 /uL to 105 /uL target molecules (20 to 2 million targets), which makes it be within the detection range in a typical clinical application environment. This dissertation also covers the design details of the CMOS microelectrode array sensor and the capacitive sensor design as a prelude to the development of the Crexens™ analyzer architecture. Finally, an expandable integrated electrochemical analyzer architecture (Crexens™) has been designed for mobile point-of-care (POC) applications. Electrochemical methods have been explored in detecting various bio-molecules such as glucose, lactate, protein, DNA, neurotransmitter, steroid hormone, which resulted in good sensitivity and selectivity. The proposed system is capable of running electrochemical experiments including cyclic voltammetry (CV), electrochemical impedance spectroscopy (EIS), electrochemical capacitive spectroscopy (ECS), amperometry, potentiometry, and other derived electrochemical based tests. This system consist of a front-end interface to sensor electrodes, a back-end user interface on smart phone and PC, a base unit as master module, a low-noise add-on module, a high-speed add-on module, and a multi-channel add-on module. The architecture allows LEGO™-like capability to stack add-on modules on to the base-unit for performance enhancements in noise, speed or parallelism. The analyzer is capable of performing up to 1900 V/s CV with 10 mV step, up to 12 kHz EIS scan range and a limit of detection at 637 pA for amperometric applications with the base module. With high performance module, the EIS scan range can be extended upto 5 MHz. The limit of detection can be further improved to be at 333 fA using the low-noise module. The form factor of the electrochemical analyzer is designed for its mobile/point-of-care applications, integrating its entire functionality on to a 70 cm² area of surface space. A glutamine enzymatic sensor was used to valid the capability of the proposed electrochemical analyzer and turned out to give good linearity and reached a limit of detection at 50 uM

Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing

How to implement quality computing with the limited power budget is the key factor to move very large scale integration (VLSI) chip design forward. This work introduces various techniques of low power VLSI design used for state of art computing. From the viewpoint of power supply, conventional in-chip voltage regulators based on analog blocks bring the large overhead of both power and area to computational chips. Motivated by this, a digital based switchable pin method to dynamically regulate power at low circuit cost has been proposed to make computing to be executed with a stable voltage supply. For one of the widely used and time consuming arithmetic units, multiplier, its operation in logarithmic domain shows an advantageous performance compared to that in binary domain considering computation latency, power and area. However, the introduced conversion error reduces the reliability of the following computation (e.g. multiplication and division.). In this work, a fast calibration method suppressing the conversion error and its VLSI implementation are proposed. The proposed logarithmic converter can be supplied by dc power to achieve fast conversion and clocked power to reduce the power dissipated during conversion. Going out of traditional computation methods and widely used static logic, neuron-like cell is also studied in this work. Using multiple input floating gate (MIFG) metal-oxide semiconductor field-effect transistor (MOSFET) based logic, a 32-bit, 16-operation arithmetic logic unit (ALU) with zipped decoding and a feedback loop is designed. The proposed ALU can reduce the switching power and has a strong driven-in capability due to coupling capacitors compared to static logic based ALU. Besides, recent neural computations bring serious challenges to digital VLSI implementation due to overload matrix multiplications and non-linear functions. An analog VLSI design which is compatible to external digital environment is proposed for the network of long short-term memory (LSTM). The entire analog based network computes much faster and has higher energy efficiency than the digital one

Photodetectors

In this book some recent advances in development of photodetectors and photodetection systems for specific applications are included. In the first section of the book nine different types of photodetectors and their characteristics are presented. Next, some theoretical aspects and simulations are discussed. The last eight chapters are devoted to the development of photodetection systems for imaging, particle size analysis, transfers of time, measurement of vibrations, magnetic field, polarization of light, and particle energy. The book is addressed to students, engineers, and researchers working in the field of photonics and advanced technologies

ECOS 2012

The 8-volume set contains the Proceedings of the 25th ECOS 2012 International Conference, Perugia, Italy, June 26th to June 29th, 2012. ECOS is an acronym for Efficiency, Cost, Optimization and Simulation (of energy conversion systems and processes), summarizing the topics covered in ECOS: Thermodynamics, Heat and Mass Transfer, Exergy and Second Law Analysis, Process Integration and Heat Exchanger Networks, Fluid Dynamics and Power Plant Components, Fuel Cells, Simulation of Energy Conversion Systems, Renewable Energies, Thermo-Economic Analysis and Optimisation, Combustion, Chemical Reactors, Carbon Capture and Sequestration, Building/Urban/Complex Energy Systems, Water Desalination and Use of Water Resources, Energy Systems- Environmental and Sustainability Issues, System Operation/ Control/Diagnosis and Prognosis, Industrial Ecology

Multi-level simulation of nano-electronic digital circuits on GPUs

Simulation of circuits and faults is an essential part in design and test validation tasks of contemporary nano-electronic digital integrated CMOS circuits. Shrinking technology processes with smaller feature sizes and strict performance and reliability requirements demand not only detailed validation of the functional properties of a design, but also accurate validation of non-functional aspects including the timing behavior. However, due to the rising complexity of the circuit behavior and the steady growth of the designs with respect to the transistor count, timing-accurate simulation of current designs requires a lot of computational effort which can only be handled by proper abstraction and a high degree of parallelization. This work presents a simulation model for scalable and accurate timing simulation of digital circuits on data-parallel graphics processing unit (GPU) accelerators. By providing compact modeling and data-structures as well as through exploiting multiple dimensions of parallelism, the simulation model enables not only fast and timing-accurate simulation at logic level, but also massively-parallel simulation with switch level accuracy. The model facilitates extensions for fast and efficient fault simulation of small delay faults at logic level, as well as first-order parametric and parasitic faults at switch level. With the parallelization on GPUs, detailed and scalable simulation is enabled that is applicable even to multi-million gate designs. This way, comprehensive analyses of realistic timing-related faults in presence of process- and parameter variations are enabled for the first time. Additional simulation efficiency is achieved by merging the presented methods in a unified simulation model, that allows to combine the unique advantages of the different levels of abstraction in a mixed-abstraction multi-level simulation flow to reach even higher speedups. Experimental results show that the implemented parallel approach achieves unprecedented simulation throughput as well as high speedup compared to conventional timing simulators. The underlying model scales for multi-million gate designs and gives detailed insights into the timing behavior of digital CMOS circuits, thereby enabling large-scale applications to aid even highly complex design and test validation tasks