16 research outputs found
Available Techniques for Magnetic Hard Disk Drive Read Channel Equalization
This paper presents an extensive, non-exhaustive, study of available hard disk drive read channel equalization techniques used in the storage and readback of magnetically stored information. The physical elements and basic principles of the storage processes are introduced together with the basic theoretical definitions and models. Both read and write processes in magnetic storage are explained along with the definition of simple key concepts such as user bit density, intersymbol interference, linear and areal density, read head pulse response models, and coding algorithm
Design of adaptive analog filters for magnetic front-end read channels
Esta tese estuda o projecto e o comportamento de filtros em tempo contínuo de
muito-alta-frequência. A motivação deste trabalho foi a investigação de soluções de filtragem
para canais de leitura em sistemas de gravação e reprodução de dados em suporte
magnético, com custos e consumo (tamanho total inferior a 1 mm2 e consumo inferior a
1mW/polo), inferiores aos circuitos existentes. Nesse sentido, tal como foi feito neste
trabalho, o rápido desenvolvimento das tecnologias de microelectrónica suscitou esforços
muito significativos a nível mundial com o objectivo de se investigarem novas técnicas
de realização de filtros em circuito integrado monolítico, especialmente em tecnologia
CMOS (Complementary Metal Oxide Semiconductor). Apresenta-se um estudo comparativo
a diversos níveis hierárquicos do projecto, que conduziu à realização e caracterização
de soluções com as características desejadas.
Num primeiro nível, este estudo aborda a questão conceptual da gravação e transmissão
de sinal bem como a escolha de bons modelos matemáticos para o tratamento da
informação e a minimização de erro inerente às aproximações na conformidade aos princípios
físicos dos dispositivos caracterizados.
O trabalho principal da tese é focado nos níveis hierárquicos da arquitectura do
canal de leitura e da realização em circuito integrado do seu bloco principal – o bloco de
filtragem. Ao nível da arquitectura do canal de leitura, apresenta-se um estudo alargado
sobre as metodologias existentes de adaptação de sinal e recuperação de dados em suporte
magnético. Este desígnio aparece no âmbito da proposta de uma solução de baixo custo,
baixo consumo, baixa tensão de alimentação e baixa complexidade, alicerçada em tecnologia
digital CMOS, para a realização de um sistema DFE (Decision Feedback Equalization)
com base na igualização de sinal utilizando filtros integrados analógicos em tempo
contínuo.
Ao nível do projecto de realização do bloco de filtragem e das técnicas de implementação
de filtros e dos seus blocos constituintes em circuito integrado, concluiu-se que
a técnica baseada em circuitos de transcondutância e condensadores, também conhecida como filtros gm-C (ou transcondutância-C), é a mais adequada para a realização de filtros
adaptativos em muito-alta-frequência. Definiram-se neste nível hierárquico mais baixo,
dois subníveis de aprofundamento do estudo no âmbito desta tese, nomeadamente: a pesquisa
e análise de estruturas ideais no projecto de filtros recorrendo a representações no
espaço de estados; e, o estudo de técnicas de realização em tecnologia digital CMOS de
circuitos de transcondutância para a implementação de filtros integrados analógicos em
tempo contínuo.
Na sequência deste estudo, apresentam-se e comparam-se duas estruturas de filtros
no espaço de estados, correspondentes a duas soluções alternativas para a realização de
um igualador adaptativo realizado por um filtro contínuo passa-tudo de terceira ordem,
para utilização num canal de leitura de dados em suporte magnético.
Como parte constituinte destes filtros, apresenta-se uma técnica de realização de
circuitos de transcondutância, e de realização de condensadores lineares usando matrizes
de transístores MOSFET para processamento de sinal em muito-alta-frequência realizada
em circuito integrado usando tecnologia digital CMOS submicrométrica. Apresentam-se
métodos de adaptação automática capazes de compensar os erros face aos valores nominais
dos componentes, devidos às tolerâncias inerentes ao processo de fabrico, para os
quais apresentamos os resultados de simulação e de medição experimental obtidos.
Na sequência deste estudo, resultou igualmente a apresentação de um circuito passível
de constituir uma solução para o controlo de posicionamento da cabeça de leitura
em sistemas de gravação/reprodução de dados em suporte magnético. O bloco proposto
é um filtro adaptativo de primeira ordem, com base nos mesmos circuitos de transcondutância
e técnicas de igualação propostos e utilizados na implementação do filtro adaptativo
de igualação do canal de leitura.
Este bloco de filtragem foi projectado e incluído num circuito integrado (Jaguar) de
controlo de posicionamento da cabeça de leitura realizado para a empresa ATMEL em
Colorado Springs, e incluído num produto comercial em parceria com uma empresa escocesa
utilizado em discos rígidos amovíveis.This thesis studies the design and behavior of continuous-time very-high-frequency
filters. The motivation of this work was the search for filtering solutions for the readchannel
in recording and reproduction of data on magnetic media systems, with costs and
consumption (total size less than 1 mm2 and consumption under 1mW/pole), lower than
the available circuits. Accordingly, as was done in this work, the rapid development of
microelectronics technology raised very significant efforts worldwide in order to investigate
new techniques for implementing such filters in monolithic integrated circuit, especially
in CMOS technology (Complementary Metal Oxide Semiconductor). We present
a comparative study on different hierarchical levels of the project, which led to the realization
and characterization of solutions with the desired characteristics.
In the first level, this study addresses the conceptual question of recording and
transmission of signal and the choice of good mathematical models for the processing of
information and minimization of error inherent in the approaches and in accordance with
the principles of the characterized physical devices.
The main work of this thesis is focused on the hierarchical levels of the architecture
of the read channel and the integrated circuit implementation of its main block - the filtering
block. At the architecture level of the read channel this work presents a comprehensive
study on existing methodologies of adaptation and signal recovery of data on
magnetic media. This project appears in the sequence of the proposed solution for a lowcost,
low consumption, low voltage, low complexity, using CMOS digital technology for
the performance of a DFE (Decision Feedback Equalization) based on the equalization of
the signal using integrated analog filters in continuous time.
At the project level of implementation of the filtering block and techniques for implementing
filters and its building components, it was concluded that the technique based
on transconductance circuits and capacitors, also known as gm-C filters is the most appropriate
for the implementation of very-high-frequency adaptive filters. We defined in
this lower level, two sub-levels of depth study for this thesis, namely: research and analysis
of optimal structures for the design of state-space filters, and the study of techniques for the design of transconductance cells in digital CMOS circuits for the implementation
of continuous time integrated analog filters.
Following this study, we present and compare two filtering structures operating in
the space of states, corresponding to two alternatives for achieving a realization of an
adaptive equalizer by the use of a continuous-time third order allpass filter, as part of a
read-channel for magnetic media devices.
As a constituent part of these filters, we present a technique for the realization of
transconductance circuits and for the implementation of linear capacitors using arrays of
MOSFET transistors for signal processing in very-high-frequency integrated circuits using
sub-micrometric CMOS technology. We present methods capable of automatic adjustment
and compensation for deviation errors in respect to the nominal values of the
components inherent to the tolerances of the fabrication process, for which we present
the simulation and experimental measurement results obtained.
Also as a result of this study, is the presentation of a circuit that provides a solution
for the control of the head positioning on recording/playback systems of data on magnetic
media. The proposed block is an adaptive first-order filter, based on the same transconductance
circuits and equalization techniques proposed and used in the implementation
of the adaptive filter for the equalization of the read channel.
This filter was designed and included in an integrated circuit (Jaguar) used to control
the positioning of the read-head done for ATMEL company in Colorado Springs, and
part of a commercial product used in removable hard drives fabricated in partnership with a Scottish company
Implementation of shingled magnetic recording towards a few grains per bit.
Master'sMASTER OF ENGINEERIN
Studies on interpolated timing recovery and external clock synchronization for magnetic recording channels
制度:新 ; 文部省報告番号:乙1909号 ; 学位の種類:博士(工学) ; 授与年月日:2004/10/28 ; 早大学位記番号:新387
Enhanced coding, clock recovery and detection for a magnetic credit card
Merged with duplicate record 10026.1/2299 on 03.04.2017 by CS (TIS)This thesis describes the background, investigation and construction of a system
for storing data on the magnetic stripe of a standard three-inch plastic credit
in: inch card. Investigation shows that the information storage limit within a 3.375 in
by 0.11 in rectangle of the stripe is bounded to about 20 kBytes. Practical issues
limit the data storage to around 300 Bytes with a low raw error rate: a four-fold
density increase over the standard. Removal of the timing jitter (that is prob-'
ably caused by the magnetic medium particle size) would increase the limit to
1500 Bytes with no other system changes. This is enough capacity for either a
small digital passport photograph or a digitized signature: making it possible
to remove printed versions from the surface of the card.
To achieve even these modest gains has required the development of a new
variable rate code that is more resilient to timing errors than other codes in its
efficiency class. The tabulation of the effects of timing errors required the construction
of a new code metric and self-recovering decoders. In addition, a new
method of timing recovery, based on the signal 'snatches' has been invented to
increase the rapidity with which a Bayesian decoder can track the changing velocity
of a hand-swiped card. The timing recovery and Bayesian detector have
been integrated into one computation (software) unit that is self-contained and
can decode a general class of (d, k) constrained codes. Additionally, the unit has
a signal truncation mechanism to alleviate some of the effects of non-linear distortion
that are present when a magnetic card is read with a magneto-resistive
magnetic sensor that has been driven beyond its bias magnetization.
While the storage density is low and the total storage capacity is meagre in
comparison with contemporary storage devices, the high density card may still
have a niche role to play in society. Nevertheless, in the face of the Smart card its
long term outlook is uncertain. However, several areas of coding and detection
under short-duration extreme conditions have brought new decoding methods
to light. The scope of these methods is not limited just to the credit card
CHANNEL CODING TECHNIQUES FOR A MULTIPLE TRACK DIGITAL MAGNETIC RECORDING SYSTEM
In magnetic recording greater area) bit packing densities are achieved through increasing
track density by reducing space between and width of the recording tracks, and/or
reducing the wavelength of the recorded information. This leads to the requirement of
higher precision tape transport mechanisms and dedicated coding circuitry.
A TMS320 10 digital signal processor is applied to a standard low-cost, low precision,
multiple-track, compact cassette tape recording system. Advanced signal processing and
coding techniques are employed to maximise recording density and to compensate for
the mechanical deficiencies of this system. Parallel software encoding/decoding
algorithms have been developed for several Run-Length Limited modulation codes. The
results for a peak detection system show that Bi-Phase L code can be reliably employed
up to a data rate of 5kbits/second/track. Development of a second system employing a
TMS32025 and sampling detection permitted the utilisation of adaptive equalisation to
slim the readback pulse. Application of conventional read equalisation techniques, that
oppose inter-symbol interference, resulted in a 30% increase in performance.
Further investigation shows that greater linear recording densities can be achieved by
employing Partial Response signalling and Maximum Likelihood Detection. Partial
response signalling schemes use controlled inter-symbol interference to increase
recording density at the expense of a multi-level read back waveform which results in an
increased noise penalty. Maximum Likelihood Sequence detection employs soft
decisions on the readback waveform to recover this loss. The associated modulation
coding techniques required for optimised operation of such a system are discussed.
Two-dimensional run-length-limited (d, ky) modulation codes provide a further means of
increasing storage capacity in multi-track recording systems. For example the code rate
of a single track run length-limited code with constraints (1, 3), such as Miller code, can
be increased by over 25% when using a 4-track two-dimensional code with the same d
constraint and with the k constraint satisfied across a number of parallel channels. The k
constraint along an individual track, kx, can be increased without loss of clock
synchronisation since the clocking information derived by frequent signal transitions
can be sub-divided across a number of, y, parallel tracks in terms of a ky constraint. This
permits more code words to be generated for a given (d, k) constraint in two dimensions
than is possible in one dimension. This coding technique is furthered by development of
a reverse enumeration scheme based on the trellis description of the (d, ky) constraints.
The application of a two-dimensional code to a high linear density system employing
extended class IV partial response signalling and maximum likelihood detection is
proposed. Finally, additional coding constraints to improve spectral response and error
performance are discussed.Hewlett Packard, Computer Peripherals Division (Bristol
On Coding and Detection Techniques for Two-Dimensional Magnetic Recording
Edited version embargoed until 15.04.2020
Full version: Access restricted permanently due to 3rd party copyright restrictions. Restriction set on 15/04/2019 by AS, Doctoral CollegeThe areal density growth of magnetic recording systems is fast approaching the superparamagnetic limit for conventional magnetic disks. This is due to the increasing demand for high data storage capacity. Two-dimensional Magnetic Recording (TDMR) is a new technology aimed at increasing the areal density of magnetic recording systems beyond the limit of current disk technology using conventional disk media. However, it relies on advanced coding and signal processing techniques to achieve areal density gains. Current state of the art signal processing for TDMR channel employed iterative decoding with Low Density Parity Check (LDPC) codes, coupled with 2D equalisers and full 2D Maximum Likelihood (ML) detectors. The shortcoming of these algorithms is their computation complexity especially with regards to the ML detectors which is exponential with respect to the number of bits involved. Therefore, robust low-complexity coding, equalisation and detection algorithms are crucial for successful future deployment of the TDMR scheme.
This present work is aimed at finding efficient and low-complexity coding, equalisation, detection and decoding techniques for improving the performance of TDMR channel and magnetic recording channel in general. A forward error correction (FEC) scheme of two concatenated single parity bit systems along track separated by an interleaver has been presented for channel with perpendicular magnetic recording (PMR) media. Joint detection decoding algorithm using constrained MAP detector for simultaneous detection and decoding of data with single parity bit system has been proposed. It is shown that using the proposed FEC scheme with the constrained MAP detector/decoder can achieve a gain of up to 3dB over un-coded MAP decoder for 1D interference channel. A further gain of 1.5 dB was achieved by concatenating two interleavers with extra parity bit when data density along track is high. The use of single bit parity code as a run length limited code as well as an error correction code is demonstrated to simplify detection complexity and improve system performance.
A low-complexity 2D detection technique for TDMR system with Shingled Magnetic Recording Media (SMR) was also proposed. The technique used the concatenation of 2D MAP detector along track with regular MAP detector across tracks to reduce the complexity order of using full 2D detection from exponential to linear. It is shown that using this technique can improve track density with limited complexity. Two methods of FEC for TDMR channel using two single parity bit systems have been discussed. One using two concatenated single parity bits along track only, separated by a Dithered Relative Prime (DRP) interleaver and the other use the single parity bits in both directions without the DRP interleaver. Consequent to the FEC coding on the channel, a 2D multi-track MAP joint detector decoder has been proposed for simultaneous detection and decoding of the coded single parity bit data. A gain of up to 5dB was achieved using the FEC scheme with the 2D multi-track MAP joint detector decoder over un-coded 2D multi-track MAP detector in TDMR channel. In a situation with high density in both directions, it is shown that FEC coding using two concatenated single parity bits along track separated by DRP interleaver performed better than when the single parity bits are used in both directions without the DRP interleaver.9mobile Nigeri
Low Power Filtering Techniques for Wideband and Wireless Applications
This dissertation presents design and implementation of continuous time analog
filters for two specific applications: wideband analog systems such as disk drive channel
and low-power wireless applications. Specific focus has been techniques that reduce the
power requirements of the overall system either through improvement in architecture or
efficiency of the analog building blocks.
The first problem that this dissertation addresses is the implementation of
wideband filters with high equalization gain. An efficient architecture that realizes
equalization zeros by combining available transfer functions associated with a
biquadratic cell is proposed. A 330MHz, 5th order Gm-C lowpass Butterworth filter with
24dB boost is designed using the proposed architecture. The prototype fabricated in
standard 0.35um CMOS process shows -41dB of IM3 for 250mV peak to peak swing
with 8.6mW/pole of power dissipation. Also, an LC prototype implemented using
similar architecture is discussed in brief. It is shown that, for practical range of frequency and SNR, LC based design is more power efficient than a Gm-C one, though
at the cost of much larger area.
Secondly, a complementary current mirror based building block is proposed,
which pushes the limits imposed by conventional transconductors on the powerefficiency
of Gm-C filters. Signal processing through complementary devices provides
good linearity and Gm/Id efficiency and is shown to improve power efficiency by nearly
7 times. A current-mode 4th order Butterworth filter is designed, in 0.13um UMC
technology, using the proposed building. It provides 54.2dB IM3 and 55dB SNR in
1.3GHz bandwidth while consuming as low as 24mW of power. All CMOS filter
realization occupies a relatively small area and is well suited for integration in deep
submicron technologies.
Thirdly, a 20MHz, 68dB dynamic range active RC filter is presented. This filter
is designed for a ten bit continuous time sigma delta ADC architecture developed
specifically for fine-line CMOS technologies. Inverter based amplification and a
common mode feedback for such amplifiers are discussed. The filter consumes 5mW of
power and occupies an area of 0.07 mm2