125 research outputs found

    Polynomial-time algorithms for generation of prime implicants

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    AbstractA notion of a neighborhood cube of a term of a Boolean function represented in the canonical disjunctive normal form is introduced. A relation between neighborhood cubes and prime implicants of a Boolean function is established. Various aspects of the problem of prime implicants generation are identified and neighborhood cube-based algorithms for their solution are developed. The correctness of algorithms is proven and their time complexity is analyzed. It is shown that all presented algorithms are polynomial in the number of minterms occurring in the canonical disjunctive normal form representation of a Boolean function. A summary of the known approaches to the solution of the problem of the generation of prime implicants is also included

    Binary decision diagrams for fault tree analysis

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    This thesis develops a new approach to fault tree analysis, namely the Binary Decision Diagram (BDD) method. Conventional qualitative fault tree analysis techniques such as the "top-down" or "bottom-up" approaches are now so well developed that further refinement is unlikely to result in vast improvements in terms of their computational capability. The BDD method has exhibited potential gains to be made in terms of speed and efficiency in determining the minimal cut sets. Further, the nature of the binary decision diagram is such that it is more suited to Boolean manipulation. The BDD method has been programmed and successfully applied to a number of benchmark fault trees. The analysis capabilities of the technique have been extended such that all quantitative fault tree top event parameters, which can be determined by conventional Kinetic Tree Theory, can now be derived directly from the BDD. Parameters such as the top event probability, frequency of occurrence and expected number of occurrences can be calculated exactly using this method, removing the need for the approximations previously required. Thus the BDD method is proven to have advantages in terms of both accuracy and efficiency. Initiator/enabler event analysis and importance measures have been incorporated to extend this method into a full analysis procedure

    Identification of the neighborhood and CA rules from spatio-temporal CA patterns

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    Extracting the rules from spatio-temporal patterns generated by the evolution of cellular automata (CA) usually produces a CA rule table without providing a clear understanding of the structure of the neighborhood or the CA rule. In this paper, a new identification method based on using a modified orthogonal least squares or CA-OLS algorithm to detect the neighborhood structure and the underlying polynomial form of the CA rules is proposed. The Quine-McCluskey method is then applied to extract minimum Boolean expressions from the polynomials. Spatio-temporal patterns produced by the evolution of 1D, 2D, and higher dimensional binary CAs are used to illustrate the new algorithm, and simulation results show that the CA-OLS algorithm can quickly select both the correct neighborhood structure and the corresponding rule

    ASTRA 3.0: Logical and Probabilistic Analysis Methods

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    This report contains the description of the main methods, implemented in ASTRA 3.0, to analyse coherent and non-coherent fault trees. ASTRA 3.0 is fully based on the Binary Decision Diagrams (BDD) approach. In case of non-coherent fault trees ASTRA 3.0 dynamically assigns to each node of the graph a label that identifies the type of the associated variable in order to drive the application of the most suitable analysis algorithms. The resulting BDD is referred to as Labelled BDD (LBDD). Exact values of the unavailability, expected number of failure and repair are calculated; the unreliability upper bound is automatically determined under given conditions. Five different importance measures of basic events are also provided. From the LBDD a ZBDD embedding all the MCS is obtained from which a subset of Significant Minimal Cut Sets (SMCS) is determined through the application of the cut-off techniques. With very complex trees it may happen that the working memory is not sufficient to store the large LBDD structure. In these cases ASTRA 3.0 completes the analysis by constructing a Reduced ZBDD embedding the SMCS - using cut-off techniques - thus by-passing the construction of the LBDD. The report also contains few tutorials on the usefulness of non-coherent fault trees, on the BDD approach, and on the determination of failure and repair frequencies.JRC.DG.G.7-Traceability and vulnerability assessmen

    ASTRA 3.x: Theoretical Manual

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    This report describes the main algorithms implemented in ASTRA 3.x to analyse coherent and non-coherent fault trees. ASTRA 3.x is fully based on the state-of-the-art of Binary Decision Diagrams (BDD) approach. In case of non-coherent fault trees ASTRA 3.x dynamically assigns to each node of the graph a label that identifies the type of the associated variable in order to drive the application of the most suitable analysis algorithms. The resulting BDD is referred to as Labelled BDD (LBDD). Exact values of the unavailability, expected number of failure and repair are calculated; the unreliability upper bound is automatically determined under given conditions. Several importance measures of basic events are also provided. From the LBDD a ZBDD embedding all MCS is obtained from which a subset of Significant Minimal Cut Sets (SMCS) is determined through the application of the cut-off techniques. An important issue is related to the analysis of safety related systems according to the IEC 61508 international standard. In order to simplify the fault tree modelling and analysis a new component type has been defined allowing determining, for any configuration, the PFDavg and PFHavg values. The Staggered testing policy is also applicable besides the Sequential testing implicitly considered by the IEC standardJRC.G.6-Security technology assessmen

    Determination of Prime Implicants for Disjunctive Boolean Functions by Use of a Digital Computer

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    Electrical Engineerin

    Spanned patterns for the logical analysis of data

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    AbstractIn a finite dataset consisting of positive and negative observations represented as real valued n-vectors, a positive (negative) pattern is an interval in Rn with the property that it contains sufficiently many positive (negative) observations, and sufficiently few negative (positive) ones. A pattern is spanned if it does not include properly any other interval containing the same set of observations. Although large collections of spanned patterns can provide highly accurate classification models within the framework of the Logical Analysis of Data, no efficient method for their generation is currently known. We propose in this paper, an incrementally polynomial time algorithm for the generation of all spanned patterns in a dataset, which runs in linear time in the output; the algorithm resembles closely the Blake and Quine consensus method for finding the prime implicants of Boolean functions. The efficiency of the proposed algorithm is tested on various publicly available datasets. In the last part of the paper, we present the results of a series of computational experiments which show the high degree of robustness of spanned patterns

    Automatic Design of Switching Networks

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    This thesis develops a method for automatically selecting an optimum set of prime implicants of a Boolean function. The optimization algorithm is based on a minimum cost of mechanization of the simplified function. A FORTRAN IV computer program to implement this approach was written and is included as part of this thesis. This program was developed within the framework of an overall theory for the automation of the design of switching networks. A programing structure as well as the theory for the automation of design is given. Also included is an outline of further areas of study which would be worth exploring as an extension of the present work

    Criteria for the Design of "fast," "safe" Asynchronous Sequential Fluidic Circuits

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    Engineerin
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