Novel Bonding technologies for wafer-level transparent packaging of MOEMS

Depending on the type of Micro-Electro-Mechanical System (MEMS), packaging costs are contributing up to 80% of the total device cost. Each MEMS device category, its function and operational environment will individually dictate the packaging requirement. Due to the lack of standardized testing procedures, the reliability of those MEMS packages sometimes can only be proven by taking into consideration its functionality over lifetime. Innovation with regards to cost reduction and standardization in the field of packaging is therefore of utmost importance to the speed of commercialisation of MEMS devices. Nowadays heavily driven by consumer applications the MEMS device market is forecasted to enjoy a compound annual growth rate (CAGR) above 13%, which is when compared to the IC device market, an outstanding growth rate. Nevertheless this forecasted value can drift upwards or downwards depending on the rate of innovation in the field of packaging. MEMS devices typically require a specific fabrication process where the device wafer is bonded to a second wafer which effectively encapsulates the MEMS structure. This method leaves the device free to move within a vacuum or an inert gas atmosphere.Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/EDA-Publishing

High Density Through Silicon Via (TSV)

The Through Silicon Via (TSV) process developed by Silex provides down to 30 micrometers pitch for through wafer connections in up to 600 micrometers thick substrates. Integrated with MEMS designs it enables significantly reduced die size and true "Wafer Level Packaging" - features that are particularly important in consumer market applications. The TSV technology also enables integration of advanced interconnect functions in optical MEMS, sensors and microfluidic devices. In addition the Via technology opens for very interesting possibilities considering integration with CMOS processing. With several companies using the process already today, qualified volume manufacturing in place and a line-up of potential users, the process is becoming a standard in the MEMS industry. We provide a introduction to the via formation process and also present some on the novel solutions made available by the technology.Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/handle/2042/16838

A Novel Nanocomposite with Photo-Polymerization for Wafer Level Application

©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or distribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder.A novel nanocomposite photo-curable material which can act both as a photoresist and a stress redistribution layer applied on the wafer level was synthesized and studied. In the experiments, 20-nm silica fillers were modified by a silane coupling agent through a hydrolysis and condensation reaction and then incorporated into the epoxy matrix. A photo-sensitive initiator was added into the formulation which can release cations after ultraviolet exposure and initiate the epoxy crosslinking reaction. The photo-crosslinking reaction of the epoxy made it a negative tone photoresist. The curing reaction of the nanocomposites was monitored by a differential scanning calorimeter with the photo-calorimetric accessory. The thermal mechanical properties of photo-cured nanocomposites thin film were also measured. It was found that the moduli change of the nanocomposites as the filler loading increasing did not follow the Mori–Tanaka model, which indicated that the nanocomposite was not a simple two-phase structure as the composite with micron size filler. The addition of nano-sized silica fillers reduced the thermal expansion and improved the stiffness of the epoxy, with only a minimal effect on the optical transparency of the epoxy, which facilitated the complete photo reaction in the epoxy

Wafer-Level Parylene Packaging With Integrated RF Electronics for Wireless Retinal Prostheses

This paper presents an embedded chip integration technology that incorporates silicon housings and flexible Parylene-based microelectromechanical systems (MEMS) devices. Accelerated-lifetime soak testing is performed in saline at elevated temperatures to study the packaging performance of Parylene C thin films. Experimental results show that the silicon chip under test is well protected by Parylene, and the lifetime of Parylenecoated metal at body temperature (37°C) is more than 60 years, indicating that Parylene C is an excellent structural and packaging material for biomedical applications. To demonstrate the proposed packaging technology, a flexible MEMS radio-frequency (RF) coil has been integrated with an RF identification (RFID) circuit die. The coil has an inductance of 16 μH with two layers of metal completely encapsulated in Parylene C, which is microfabricated using a Parylene–metal–Parylene thin-film technology. The chip is a commercially available read-only RFID chip with a typical operating frequency of 125 kHz. The functionality of the embedded chip has been tested using an RFID reader module in both air and saline, demonstrating successful power and data transmission through the MEMS coil

A Fully Parameterized Fem Model for Electromagnetic Optimization of an RF Mems Wafer Level Package

In this work, we present a fully parameterized capped transmission line model for electromagnetic optimization of a wafer level package (WLP) for RF MEMS applications using the Ansoft HFSS-TM electromagnetic simulator. All the degrees of freedom (DoF's) in the package fabrication can be modified within the model in order to optimize for losses and mismatch (capacitive and inductive couplings) introduced by the cap affecting the MEMS RF behaviour. Ansoft HFSS-TM was also validated for the simulation of capped RF MEMS devices by comparison against experimental data. A test run of capped 50 transmission lines and shorts was fabricated and tested.Comment: Submitted on behalf of EDA Publishing Association (http://irevues.inist.fr/EDA-Publishing

Extending systems-on-chip to the third dimension : performance, cost and technological tradeoffs.

Because of the today's market demand for high-performance, high-density portable hand-held applications, electronic system design technology has shifted the focus from 2-D planar SoC single-chip solutions to different alternative options as tiled silicon and single-level embedded modules as well as 3-D integration. Among the various choices, finding an optimal solution for system implementation dealt usually with cost, performance and other technological trade-off analysis at the system conceptual level. It has been identified that the decisions made within the first 20% of the total design cycle time will ultimately result up to 80% of the final product cost. In this paper, we discuss appropriate and realistic metric for performance and cost trade-off analysis both at system conceptual level (up-front in the design phase) and at implementation phase for verification in the three-dimensional integration. In order to validate the methodology, two ubiquitous electronic systems are analyzed under various implementation schemes and discuss the pros and cons of each of them

Thin Film Encapsulation of Radio Frequency (RF) Microelectromechanical Systems (MEMS) Switches

Microelectromechanical systems (MEMS) radio frequency (RF) switches have been shown to have excellent electrical performance over a wide range of frequencies. However, cost-effective packaging techniques for MEMS switches do not currently exist. This thesis involves the design of RF-optimized encapsulations consisting of dielectric and metal layers, and the creation of a novel thin film encapsulation process to fabricate the encapsulations. The RF performance of several encapsulation designs are evaluated with an analytical model, full wave electromagnetic simulation, and laboratory testing. Performance degradation due to parasitic and reflection losses due to the package is considered, and RF feed-throughs of the transmission line into and out of the package are designed and assessed. Ten different encapsulation designs were created and their RF performance was characterized in terms of insertion loss, return loss, and isolation. A switch without an encapsulation and a switch with a dielectric encapsulation were fabricated and tested by the Air Force Research Laboratory (AFRL), and the test data was used to verify the data from analytical modeling and electromagnetic simulation performed in this work. All results were used to design an optimized encapsulation. An RF MEMS switch with this encapsulation was shown to have an overall insertion loss of less than -0.15 dB at 20 GHz compared to an unencapsulated switch insertion loss of about -0.1 dB. The isolation of the switch was slightly improved with the encapsulation. The fabrication process proposed to manufacture these encapsulations uses a low temperature solder as the metal encapsulation layer. As the final step in the fabrication, the solder is brought to melting temperature and reflowed over the etch holes to form a hermetic encapsulation

High performance 3-folded symmetric decoupled MEMS gyroscopes

This thesis reports, for the first time, on a novel design and architecture for realizing inertial grade gyroscope based on Micro-Electro-Mechanical Systems (MEMS) technology. The proposed device is suitable for high-precision Inertial Navigation Systems (INS). The new design has been investigated analytically and numerically by means of Finite Element Modeling (FEM) of the shapes, resonance frequencies and decoupling of the natural drive and sense modes of the various implementations. Also, famous phenomena known as spring softening and spring hardening are studied. Their effect on the gyroscope operation is modeled numerically in Matlab/Simulink platform. This latter model is used to predict the drive/sense mode matching capability of the proposed designs. Based on the comparison with the best recently reported performance towards inertial grade operation, it is expected that the novel architecture further lowers the dominant Brownian (thermo-mechanical) noise level by more than an order of magnitude (down to 0.08º/hr). Moreover, the gyroscope\u27s figure of merit, such as output sensitivity (150 mV/º/s), is expected to be improved by more than two orders of magnitude. This necessarily results in a signal to noise ratio (SNR) which is up to three orders of magnitude higher (up to 1,900mV/ º/hr). Furthermore, the novel concept introduced in this work for building MEMS gyroscopes allows reducing the sense parasitic capacitance by up to an order of magnitude. This in turn reduces the drive mode coupling or quadrature errors in the sensor\u27s output signal. The new approach employs Silicon-on-Insulator (SOI) substrates that allows the realization of large mass (\u3e1.6mg), large sense capacitance (\u3e2.2pF), high quality factors (\u3e21,000), large drive amplitude (~2-4 µm) and low resonance frequency (~3-4 KHz) as well as the consequently suppressed noise floor and reduced support losses for high-performance vacuum operation. Several challenges were encountered during fabrication that required developing high aspect ratio (up to 1:20) etching process for deep trenches (up to 500 µm). Frequency Response measurement platform was built for devices characterization. The measurements were performed at atmospheric pressures causing huge drop of the devices performance. Therefore, various MEMS gyroscope packaging technologies are studied. Wafer Level Packaging (WLP) is selected to encapsulate the fabricated devices under vacuum by utilizing wafer bonding. Through Silicon Via (TSV) technology was developed (as connections) to transfer the electrical signals (of the fabricated devices) outside the cap wafers

Wafer-level vacuum sealing for packaging of silicon photonic MEMS

Silicon (Si) photonic micro-electro-mechanical systems (MEMS), with its low-power phase shifters and tunable couplers, is emerging as a promising technology for large-scale reconfigurable photonics with potential applications for example in photonic accelerators for artificial intelligence (AI) workloads. For silicon photonic MEMS devices, hermetic/vacuum packaging is crucial to the performance and longevity, and to protect the photonic devices from contamination. Here, we demonstrate a wafer-level vacuum packaging approach to hermetically seal Si photonic MEMS wafers produced in the iSiPP50G Si photonics foundry platform of IMEC. The packaging approach consists of transfer bonding and sealing the silicon photonic MEMS devices with 30 μm-thick Si caps, which were prefabricated on a 100 mm-diameter silicon-on-insulator (SOI) wafer. The packaging process achieved successful wafer-scale vacuum sealing of various photonic devices. The functionality of photonic MEMS after the hermetic/vacuum packaging was confirmed. Thus, the demonstrated thin Si cap packaging shows the possibility of a novel vacuum sealing method for MEMS integrated in standard Si photonics platforms

III/V-on-Si MQW lasers by using a novel photonic integration method of regrowth on a bonding template.

Silicon photonics is becoming a mainstream data-transmission solution for next-generation data centers, high-performance computers, and many emerging applications. The inefficiency of light emission in silicon still requires the integration of a III/V laser chip or optical gain materials onto a silicon substrate. A number of integration approaches, including flip-chip bonding, molecule or polymer wafer bonding, and monolithic III/V epitaxy, have been extensively explored in the past decade. Here, we demonstrate a novel photonic integration method of epitaxial regrowth of III/V on a III/V-on-SOI bonding template to realize heterogeneous lasers on silicon. This method decouples the correlated root causes, i.e., lattice, thermal, and domain mismatches, which are all responsible for a large number of detrimental dislocations in the heteroepitaxy process. The grown multi-quantum well vertical p-i-n diode laser structure shows a significantly low dislocation density of 9.5 × 104 cm-2, two orders of magnitude lower than the state-of-the-art conventional monolithic growth on Si. This low dislocation density would eliminate defect-induced laser lifetime concerns for practical applications. The fabricated lasers show room-temperature pulsed and continuous-wave lasing at 1.31 μm, with a minimal threshold current density of 813 A/cm2. This generic concept can be applied to other material systems to provide higher integration density, more functionalities and lower total cost for photonics as well as microelectronics, MEMS, and many other applications