Low energy digital circuits in advanced nanometer technologies

The demand for portable devices and the continuing trend towards the Internet ofThings (IoT) have made of energy consumption one of the main concerns in the industry and researchers. The most efficient way of reducing the energy consump-tion of digital circuits is decreasing the supply voltage (Vdd) since the dynamicenergy quadratically depends onVdd. Several works have shown that an optimumsupply voltage exists that minimizes the energy consumption of digital circuits. This optimum supply voltage is usually around 200 mV and 400 mV dependingon the circuit and technology used. To obtain these low supply voltages, on-chipdc-dc converters with high efficiency are needed.This thesis focuses on the study of subthreshold digital systems in advancednanometer technologies. These systems usually can be divided into a Power Man-agement Unit (PMU) and a digital circuit operating at the subthreshold regime.In particular, while considering the PMU, one of the key circuits is the dc-dcconverter. This block converts the voltage from the power source (battery, supercapacitor or wireless power transfer link) to a voltage between 200 mV and 400mV in order to power the digital circuit. In this thesis, we developed two chargerecycling techniques in order to improve the efficiency of switched capacitors dc-dcconverters. The first one is based on a technique used in adiabatic circuits calledstepwise charging. This technique was used in circuits and applications wherethe switching consumption of a big capacitance is very important. We analyzedthe possibility of using this technique in switched capacitor dc-dc converters withintegrated capacitors. We showed through measurements that a 29% reductionin the gate drive losses can be obtained with this technique. The second one isa simplification of stepwise charging which can be applied in some architecturesof switched capacitors dc-dc converters. We also fabricated and tested a dc-dcconverter with this technique and obtained a 25% energy reduction in the drivingof the switches that implement the converter.Furthermore, we studied the digital circuit working in the subthreshold regime,in particular, operating at the minimum energy point. We studied different modelsfor circuits working in these conditions and improved them by considering thedifferences between the NMOS and PMOS transistors. We obtained an optimumNMOS/PMOS leakage current imbalance that minimizes the total leakage energy per operation. This optimum depends on the architecture of the digital circuitand the input data. However, we also showed that important energy reductionscan be obtained by operating at a mean optimum imbalance. We proposed two techniques to achieve the optimum imbalance. We used aFully Depleted Silicon on Insulator (FD-SOI) 28 nm technology for most of the simulations, but we also show that these techniques can be applied in traditionalbulk CMOS technologies. The first one consists in using the back plane voltage of the transistors (or bulk voltage in traditional CMOS) to adjust independently theleakage current of the NMOS and PMOS transistor to work under the optimum NMOS/PMOS leakage current imbalance. We called this approach the OptimumBack Plane Biasing (OBB). A second technique consists of using the length of the transistors to adjust this leakage current imbalance. In the subthreshold regimeand in advanced nanometer technologies a moderate increase in the length has little impact in the output capacitance of the gates and thus in the dynamic energy.We called this approach an Asymmetric Length Biasing (ALB). Finally, we use these techniques in some basic circuits such as adders. We show that around 50% energy reduction can be obtained, in a wide range of frequency while working near the minimum energy point and using these techniques. The main contributions of this thesis are: • Analysis of the stepwise charging technique in small capacitances. •Implementation of stepwise charging technique as a charge recycling tech-nique for efficiency improvement in switched capacitor dc-dc converters. • Development of a charge sharing technique for efficiency improvement inswitched capacitor dc-dc converters. • Analysis of minimum operating voltage of digital circuits due to intrinsicnoise and the impact of technology scaling in this minimum. • Improvement in the modeling of the minimum energy point while considering NMOS and PMOS transistors difference. • Demonstration of the existence of an optimum leakage current imbalance be-tween the NMOS and PMOS transistors that minimizes energy consumptionin the subthreshold regiion. • Development of a back plane (bulk) voltage strategy for working in this optimum.• Development of a sizing strategy for working in the aforementioned optimum. • Analysis of the impact of architecture and input data on the optimum im-balance. The thesis is based on the publications [1–8]. During the Ph.D. program, other publications were generated [9–16] that are partially related with the thesis butwere not included in it.La constante demanda de dispositivos portables y los avances hacia la Internet de las Cosas han hecho del consumo de energía uno de los mayores desafíos y preocupación en la industria y la academia. La forma más eficiente de reducir el consumo de energía de los circuitos digitales es reduciendo su voltaje de alimentación ya que la energía dinámica depende de manera cuadrática con dicho voltaje. Varios trabajos demostraron que existe un voltaje de alimentación óptimo, que minimiza la energía consumida para realizar cierta operación en un circuito digital, llamado punto de mínima energía. Este óptimo voltaje se encuentra usualmente entre 200 mV y 400 mV dependiendo del circuito y de la tecnología utilizada. Para obtener estos voltajes de alimentación de la fuente de energía, se necesitan conversores dc-dc integrados con alta eficiencia. Esta tesis se concentra en el estudio de sistemas digitales trabajando en la región sub umbral diseñados en tecnologías nanométricas avanzadas (28 nm). Estos sistemas se pueden dividir usualmente en dos bloques, uno llamado bloque de manejo de potencia, y el segundo, el circuito digital operando en la region sub umbral. En particular, en lo que corresponde al bloque de manejo de potencia, el circuito más crítico es en general el conversor dc-dc. Este circuito convierte el voltaje de una batería (o super capacitor o enlace de transferencia inalámbrica de energía o unidad de cosechado de energía) en un voltaje entre 200 mV y 400 mV para alimentar el circuito digital en su voltaje óptimo. En esta tesis desarrollamos dos técnicas que, mediante el reciclado de carga, mejoran la eficiencia de los conversores dc-dc a capacitores conmutados. La primera es basada en una técnica utilizada en circuitos adiabáticos que se llama carga gradual o a pasos. Esta técnica se ha utilizado en circuitos y aplicaciones en donde el consumo por la carga y descarga de una capacidad grande es dominante. Nosotros analizamos la posibilidad de utilizar esta técnica en conversores dc-dc a capacitores conmutados con capacitores integrados. Se demostró a través de medidas que se puede reducir en un 29% el consumo debido al encendido y apagado de las llaves que implementan el conversor dc-dc. La segunda técnica, es una simplificación de la primera, la cual puede ser aplicada en ciertas arquitecturas de conversores dc-dc a capacitores conmutados. También se fabricó y midió un conversor con esta técnica y se obtuvo una reducción del 25% en la energía consumida por el manejo de las llaves del conversor. Por otro lado, estudiamos los circuitos digitales operando en la región sub umbral y en particular cerca del punto de mínima energía. Estudiamos diferentes modelos para circuitos operando en estas condiciones y los mejoramos considerando las diferencias entre los transistores NMOS y PMOS. Mediante este modelo demostramos que existe un óptimo en la relación entre las corrientes de fuga de ambos transistores que minimiza la energía de fuga consumida por operación. Este óptimo depende de la arquitectura del circuito digital y ademas de los datos de entrada del circuito. Sin embargo, demostramos que se puede reducir el consumo de manera considerable al operar en un óptimo promedio. Propusimos dos técnicas para alcanzar la relación óptima. Utilizamos una tecnología FD-SOI de 28nm para la mayoría de las simulaciones, pero también mostramos que estas técnicas pueden ser utilizadas en tecnologías bulk convencionales. La primer técnica, consiste en utilizar el voltaje de la puerta trasera (o sustrato en CMOS convencional) para ajustar de manera independiente las corrientes del NMOS y PMOS para que el circuito trabaje en el óptimo de la relación de corrientes. Esta técnica la llamamos polarización de voltaje de puerta trasera óptimo. La segunda técnica, consiste en utilizar los largos de los transistores para ajustar las corrientes de fugas de cada transistor y obtener la relación óptima. Trabajando en la región sub umbral y en tecnologías avanzadas, incrementar moderadamente el largo del transistor tiene poco impacto en la energía dinámica y es por eso que se puede utilizar. Finalmente, utilizamos estas técnicas en circuitos básicos como sumadores y mostramos que se puede obtener una reducción de la energía consumida de aproximadamente 50%, en un amplio rango de frecuencias, mientras estos circuitos trabajan cerca del punto de energía mínima. Las principales contribuciones de la tesis son: • Análisis de la técnica de carga gradual o a pasos en capacidades pequeñas. • Implementación de la técnica de carga gradual para la mejora de eficiencia de conversores dc-dc a capacitores conmutados. • Simplificación de la técnica de carga gradual para mejora de la eficiencia en algunas arquitecturas de conversores dc-dc de capacitores conmutados. • Análisis del mínimo voltaje de operación en circuitos digitales debido al ruido intrínseco del dispositivo y el impacto del escalado de las tecnologías en el mismo. • Mejoras en el modelado del punto de energía mínima de operación de un circuito digital en el cual se consideran las diferencias entre el transistor PMOS y NMOS. • Demostración de la existencia de un óptimo en la relación entre las corrientes de fuga entre el NMOS y PMOS que minimiza la energía de fugas consumida en la región sub umbral. • Desarrollo de una estrategia de polarización del voltaje de puerta trasera para que el circuito digital trabaje en el óptimo antes mencionado. • Desarrollo de una estrategia para el dimensionado de los transistores que componen las compuertas digitales que permite al circuito digital operar en el óptimo antes mencionado. • Análisis del impacto de la arquitectura del circuito y de los datos de entrada del mismo en el óptimo antes mencionado

Impact of intrinsic parameter fluctuations in ultra-thin body silicon-on-insulator MOSFET on 6-transistor SRAM cell

As CMOS device dimensions are being aggressively scaled, the device characteristic must be assessed against fundamental physical limits. Nanoscale device modelling and statistical circuit analysis is needed to provide designer with ability to explore innovative new MOSFET devices as well as understanding the limits of the scaling process. This work introduces a systematic simulation methodology to investigate the impact of intrinsic parameter fluctuation for a novel Ultra-Thin-Body (UTB) Silicon-on-Insulator (SOI) transistor on the corresponding device and circuits. It provides essential link between physical device-level numerical simulation and circuit-level simulation. A systematic analysis of the effects of random discrete dopants, body thickness variations and line edge roughness on a well scaled 10 nm, 7.5 nm and 5 nm channel length UTB-SOI MOSFET is performed. To fully realise the performance benefits of UTB-SOI based SRAM cells a statistical circuit simulation methodology which can fully capture intrinsic parameter fluctuations information into the compact model is developed. The impact of intrinsic parameter fluctuations on the stability and performance of 6T SRAM has been investigated. A comparison with the behaviour of a 6T SRAM based on a conventional 35 nm MOSFET is also presented

Energy Efficient RF Transmitter Design using Enhanced Breakdown Voltage SOI-CMOS Compatible MESFETs

abstract: The high cut-off frequency of deep sub-micron CMOS technologies has enabled the integration of radio frequency (RF) transceivers with digital circuits. However, the challenging point is the integration of RF power amplifiers, mainly due to the low breakdown voltage of CMOS transistors. Silicon-on-insulator (SOI) metal semiconductor field effect transistors (MESFETs) have been introduced to remedy the limited headroom concern in CMOS technologies. The MESFETs presented in this thesis have been fabricated on different SOI-CMOS processes without making any change to the standard fabrication steps and offer 2-30 times higher breakdown voltage than the MOSFETs on the same process. This thesis explains the design steps of high efficiency and wideband RF transmitters using the proposed SOI-CMOS compatible MESFETs. This task involves DC and RF characterization of MESFET devices, along with providing a compact Spice model for simulation purposes. This thesis presents the design of several SOI-MESFET RF power amplifiers operating at 433, 900 and 1800 MHz with ~40% bandwidth. Measurement results show a peak power added efficiency (PAE) of 55% and a peak output power of 22.5 dBm. The RF-PAs were designed to operate in Class-AB mode to minimize the linearity degradation. Class-AB power amplifiers lead to poor power added efficiency, especially when fed with signals with high peak to average power ratio (PAPR) such as wideband code division multiple access (W-CDMA). Polar transmitters have been introduced to improve the efficiency of RF-PAs at backed-off powers. A MESFET based envelope tracking (ET) polar transmitter was designed and measured. A low drop-out voltage regulator (LDO) was used as the supply modulator of this polar transmitter. MESFETs are depletion mode devices; therefore, they can be configured in a source follower configuration to have better stability and higher bandwidth that MOSFET based LDOs. Measurement results show 350 MHz bandwidth while driving a 10 pF capacitive load. A novel polar transmitter is introduced in this thesis to alleviate some of the limitations associated with polar transmitters. The proposed architecture uses the backgate terminal of a partially depleted transistor on SOI process, which relaxes the bandwidth and efficiency requirements of the envelope amplifier in a polar transmitter. The measurement results of the proposed transmitter demonstrate more than three times PAE improvement at 6-dB backed-off output power, compared to the traditional RF transmitters.Dissertation/ThesisPh.D. Electrical Engineering 201

Statistical circuit simulations - from ‘atomistic’ compact models to statistical standard cell characterisation

This thesis describes the development and application of statistical circuit simulation methodologies to analyse digital circuits subject to intrinsic parameter fluctuations. The specific nature of intrinsic parameter fluctuations are discussed, and we explain the crucial importance to the semiconductor industry of developing design tools which accurately account for their effects. Current work in the area is reviewed, and three important factors are made clear: any statistical circuit simulation methodology must be based on physically correct, predictive models of device variability; the statistical compact models describing device operation must be characterised for accurate transient analysis of circuits; analysis must be carried out on realistic circuit components. Improving on previous efforts in the field, we posit a statistical circuit simulation methodology which accounts for all three of these factors. The established 3-D Glasgow atomistic simulator is employed to predict electrical characteristics for devices aimed at digital circuit applications, with gate lengths from 35 nm to 13 nm. Using these electrical characteristics, extraction of BSIM4 compact models is carried out and their accuracy in performing transient analysis using SPICE is validated against well characterised mixed-mode TCAD simulation results for 35 nm devices. Static d.c. simulations are performed to test the methodology, and a useful analytic model to predict hard logic fault limitations on CMOS supply voltage scaling is derived as part of this work. Using our toolset, the effect of statistical variability introduced by random discrete dopants on the dynamic behaviour of inverters is studied in detail. As devices scaled, dynamic noise margin variation of an inverter is increased and higher output load or input slew rate improves the noise margins and its variation. Intrinsic delay variation based on CV/I delay metric is also compared using ION and IEFF definitions where the best estimate is obtained when considering ION and input transition time variations. Critical delay distribution of a path is also investigated where it is shown non-Gaussian. Finally, the impact of the cell input slew rate definition on the accuracy of the inverter cell timing characterisation in NLDM format is investigated

Caractérisation électrique et modélisation du transport dans matériaux et dispositifs SOI avancés

This thesis is dedicated to the electrical characterization and transport modeling in advanced SOImaterials and devices for ultimate micro-nano-electronics. SOI technology is an efficient solution tothe technical challenges facing further downscaling and integration. Our goal was to developappropriate characterization methods and determine the key parameters. Firstly, the conventionalpseudo-MOSFET characterization was extended to heavily-doped SOI wafers and an adapted modelfor parameters extraction was proposed. We developed a nondestructive electrical method to estimatethe quality of bonding interface in metal-bonded wafers for 3D integration. In ultra-thin fully-depletedSOI MOSFETs, we evidenced the parasitic bipolar effect induced by band-to-band tunneling, andproposed new methods to extract the bipolar gain. We investigated multiple-gate transistors byfocusing on the coupling effect in inversion-mode vertical double-gate SOI FinFETs. An analyticalmodel was proposed and subsequently adapted to the full depletion region of junctionless SOI FinFETs.We also proposed a compact model of carrier profile and adequate parameter extraction techniques forjunctionless nanowires.Cette thèse est consacrée à la caractérisation et la modélisation du transport électronique dans des matériaux et dispositifs SOI avancés pour la microélectronique. Tous les matériaux innovants étudiés(ex: SOI fortement dopé, plaques obtenues par collage etc.) et les dispositifs SOI sont des solutions possibles aux défis technologiques liés à la réduction de taille et à l'intégration. Dans ce contexte,l'extraction des paramètres électriques clés, comme la mobilité, la tension de seuil et les courants de fuite est importante. Tout d'abord, la caractérisation classique pseudo-MOSFET a été étendue aux plaques SOI fortement dopées et un modèle adapté pour l'extraction de paramètres a été proposé. Nous avons également développé une méthode électrique pour estimer la qualité de l'interface de collage pour des plaquettes métalliques. Nous avons montré l'effet bipolaire parasite dans des MOSFET SOI totalement désertés. Il est induit par l’effet tunnel bande-à-bande et peut être entièrement supprimé par une polarisation arrière. Sur cette base, une nouvelle méthode a été développée pour extraire le gain bipolaire. Enfin, nous avons étudié l'effet de couplage dans le FinFET SOI double grille, en mode d’inversion. Un modèle analytique a été proposé et a été ensuite adapté aux FinFETs sans jonction(junctionless). Nous avons mis au point un modèle compact pour le profil des porteurs et des techniques d’extraction de paramètres