263 research outputs found

    A sectorial scheme of gate-all-around field effect transistor with improved electrical characteristics

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    Reliability and controllability for a new scheme of gate-all-around field effect transistor (GAA-FET) with a silicon channel utilizing a sectorial cross section is evaluated in terms of Ion/Ioff current ratio, transconductance, subthreshold slope, threshold voltage roll-off, and drain induced barrier lowering (DIBL). In addition, the scaling behavior of electronic figures of merit is comprehensively studied with the aid of physical simulations. The electrical characteristic of proposed structure is compared with a circular GAA-FET, which is previously calibrated with an IBM sample at the 22 nm channel length using 3D-TCAD simulations. Our simulation results show that sectorial cross section GAA-FET is a superior structure for controlling short channel effects (SCEs) and to obtain better performance compared to conventional circular cross section counterpart

    Compact DC Modeling of Tunnel-FETs

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    En l'última dècada, el transistor d'efecte de camp amb efecte túnel (TFET) ha guanyat molt interès i es maneja com un possible successor de la tecnologia MOSFET convencional. El transport de càrrega en un TFET es basa en el mecanisme de túnel de banda a banda (B2B) i, per tant, el pendent sub-llindar a temperatura ambient pot superar el límit de 60 mV / dec. Per descriure i analitzar el comportament del TFET en les simulacions de circuits, aquesta dissertació introdueix un model compacte de CC per TFET de doble comporta. L'enfocament de modelatge considera l'efecte túnel B2B amb l'efecte parasitari del corrent túnel assistida per trampes (TAT) en l'estat ON i ambipolar del TFET. Inclou un paquet d'equacions compactes per al potencial 2D per descriure el diagrama de banda del TFET. Basat en el diagrama de banda, el B2B i el corrent TAT es deriven per separat. Per fer-ho, primer es troba una expressió compacta per la llargada túnel, que després s'utilitza juntament amb un enfocament numèric robust de tipus Wentzel-Kramers-Brillouin (WKB) per calcular la probabilitat túnel. Després, usant l'equació de túnel de Landauer, la taxa de generació túnel es calcula i s'aproxima per arribar a una expressió de forma tancada per a la densitat de corrent. Amb una aproximació addicional de la densitat de corrent utilitzant una funció matemàtica, s'aconsegueixen expressions compactes per al túnel B2B resultant i el corrent TAT. La verificació del model es realitza amb l'ajuda de les dades de simulació TCAD Sentaurus per diverses configuracions de simulació. A més, la validesa del model es demostra mitjançant mesuraments de TFET complementaris fabricats. Per demostrar l'estabilitat numèrica i la continuïtat, així com la flexibilitat, es realitzen i analitzen simulacions de circuits lògics basats en TFET com un inversor d'una sola etapa o una cel·la SRAM. La combinació del model CC amb un model TFET AC permet una simulació transitòria d'un oscil·lador en anell de 11 etapes.En la última década, el transistor de efecto de campo con efecto túnel (TFET) ha ganado mucho interés y se maneja como un posible sucesor de la tecnología MOSFET convencional. El transporte de carga en un TFET se basa en el mecanismo de túnel de banda a banda (B2B) y, por lo tanto, la pendiente sub-umbral a temperatura ambiente puede superar el límite de 60 mV / dec. Para describir y analizar el comportamiento del TFET en las simulaciones de circuitos, esta disertación introduce un modelo compacto de CC para TFET de doble compuerta. El enfoque de modelado considera el efecto túnel B2B con el efecto parasitario de la corriente túnel asistida por trampas (TAT) en el estado ON y AMBIPOLAR del TFET. Incluye un paquete de ecuaciones compactas del potencial 2D para describir el diagrama de banda del TFET. Basado en el diagrama de banda, el B2B y la corriente TAT se derivan por separado. Para hacerlo, primero se encuentra una expresión compacta para la longitud túnel, que luego se utiliza junto con un enfoque numérico robusto de tipo Wentzel-Kramers-Brillouin (WKB) para calcular la probabilidad túnel. Luego, usando la ecuación de túnel de Landauer, la tasa de generación túnel se calcula y aproxima para llegar a una expresión de forma cerrada para la densidad de corriente. Con una aproximación adicional de la densidad de corriente por una función matemática, se logran expresiones compactas para el túnel B2B resultante y la corriente TAT. La verificación del modelo se realiza con la ayuda de los datos de simulación TCAD Sentaurus para varias configuraciones de simulación. Además, la validez del modelo se demuestra mediante mediciones de TFET complementarios fabricados. Para demostrar la estabilidad numérica y la continuidad, así como la flexibilidad, se realizan y analizan simulaciones de circuitos lógicos basados en TFET como un inversor de una sola etapa o una celda SRAM. La combinación del modelo CC con un modelo TFET AC permite una simulación transitoria de un oscilador en anillo de 11 etapas.In the last decade, the tunnel field-effect transistor (TFET) has gained a lot of interest and is handled as a possible successor of the conventional MOSFET technology. The current transport of a TFET is based on the band-to-band (B2B) tunneling mechanism and therefore, the subthreshold slope at room temperature can overcome the limit of 60 mV/dec. In order to describe and analyze the TFET behavior in circuit simulations, this dissertation introduces a compact DC model for double-gate TFETs. The modeling approach considers the B2B tunneling and the parasitic effect of trap-assisted tunneling (TAT) in the ON- and AMBIPOLAR-state of the TFET. It includes a 2D compact potential equation package to de-scribe the band diagram of the TFET. Based on the band diagram, the B2B tunneling and TAT current part are derived separately. In order to do so, firstly a compact expression for the tunneling length is found, which is then used together with a numerical robust Wentzel-Kramers-Brillouin (WKB) approach to calculate the tunneling probability. Afterwards, using Landauer’s tunneling equation, the tunneling generation rate is calculated and approximated to come to a closed-form expression for the current density. Further approximation of the current density by a mathematical function, compact expressions for the resulting B2B tun-neling and TAT current are achieved. The verification of the model is done with the help of TCAD Sentaurus simulation data for various simulation setups. Furthermore, the validity of the model is proven by measurements of fabricated complementary TFETs. In order to demonstrate the numerical stability and continuity as well as the flexibility, simulations of TFET-based logic circuits like a single-stage inverter or an SRAM cell are performed and analyzed. The combination of the DC model with an TFET AC model allows for a transient simulation of an 11-stage ring oscillator

    Two-Dimensional Analytical Modeling of Tunnel-FETs

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    Basat en un mecanisme de transport de corrent de banda a banda, el túnel-FET és capaç de superar la limitació de pendent sub-llindar física del MOSFET de 60 mV /dec. Per tant, s'ha convertit en un dels dispositius més prometedors per ser el successor del MOSFET clàssic en els últims anys. Aquesta tesi descriu tots els passos necessaris per modelar analíticament un Túnel-FET de doble porta. El model inclou una solució electrostàtica de dues dimensions en totes les regions del dispositiu, el que permet fins i tot simulacions hetero-unió del dispositiu. Per a un comportament més realista del dispositiu, cal tenir en compte el rendiment del dispositiu que limita els perfils de dopatge de forma Gaussiana en les unions del canal. Les expressions per a les probabilitats de túnel de banda a banda i les de Trap-Assisted-Tunneling (TAT) són executades per un enfocament WKB quasi bidimensional. El corrent del dispositiu es calcula mitjançant la teoria de transmissió de Landauer. El model és vàlid per a dispositius de canal curt i les estàncies estan ben comparades amb les dades de simulació TCAD Sentaurus i amb les medicions proporcionades. S'introdueix un modelo general per les flactuacions del dopant aleatoria, que prediu les influencies característiques del dispositiu en el corrent de sortida i el voltatge llindar. El model s'aplica al MOSFET, així com a dispositius TFET.Basado en un mecanismo de transporte de corriente banda a banda, el Tunnel-FET es capaz de superar la limitación de pendiente sub-umbral física del MOSFET de 60 mV/dec. Por lo tanto, esto lo convierte en uno de los dispositivos más prometedores para ser el sucesor del MOSFET clásico en los últimos años. Esta tesis describe todos los pasos necesarios para modelar analíticamente un Tunnel-FET de doble puerta. El modelo incluye una solución electrostática bidimensional en todas las regiones del dispositivo, lo que permite incluso simulaciones de hetero-unión del dispositivo. Para un comportamiento más realista del dispositivo se tiene en cuenta el rendimiento del dispositivo que limita los perfiles de dopaje de forma Gaussiana en las uniones del canal. Las expresiones para las probabilidades de túnel de banda a banda y de Trap-Assisted-Tunneling (TAT) se implementan mediante un enfoque de WKB cuasi bidimensional. La corriente del dispositivo se calcula mediante la teoría de transmisión de Landauer. El modelo es válido para dispositivos de canal corto y las estancias están bien comparadas con los datos de simulación TCAD Sentaurus y con las mediciones proporcionadas. Se introduce un modelo general para las fluctuaciones del dopado aleatorio, que predice las influencias características del dispositivo en la corriente de salida y el voltaje umbral. El modelo se aplica al MOSFET, así como a los dispositivos TFET.Based on a band-to-band current transport mechanism, the Tunnel-FET is able to overcome the physical subthreshold slope limitation of the MOSFET of 60 mV/dec. Therefore, it has become one of the most promising devices to be the successor of the classical MOSFET in the last few years. This thesis describes all necessary steps to analytically model a double-gate Tunnel-FET. The model includes a two-dimensional electrostatic solution in all device regions, which enables even hetero-junction device simulations. Device performance limiting Gaussian-shaped doping profiles at the channel junctions are taken into account for a realistic device behavior. Expressions for the band-to-band and trap-assisted-tunneling probabilities are implemented by a quasi two-dimensional WKB approach. The device current is calculated based on Landauer's transmission theory. The model is valid for short-channel devices and stays is good agreement with the TCAD Sentaurus simulation data and with the provided measurements. A general model for random-dopant-fluctuations is introduced, which predicts characteristic device influences on the output current and threshold voltage. The model is applied to MOSFET, as well as TFET devices

    높은 전류구동능력을 위한 Si/SiGe 물질을 가지는 터널링 전계효과 트랜지스터

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    학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 2. 박병국.For integrated circuits with highly-scaled complementary MOS (CMOS) technology, power dissipation problem has become an important issue since power per chip continues to increases and leakage power dominates in advanced technology nodes. In order to solve power issues, the supply voltage (VDD) scaling is very essential and devices which have low leakage current are needed. Recently, many research groups have studied a tunnel field-effect transistors (tunnel FETs) which is suitable for low operating power device. Tunnel FETs have very low leakage current and small subthrehold swing (SS) at room temperature unlike CMOS because of carrier injection using tunneling. In this thesis, a novel tunnel FET with SiGe body and elevated Si drain region have been proposed. The proposed tunnel FET has larger current drivability than conventional Si tunnel FETs because it uses a narrow bandgap material for low tunneling resistance. Also, it is expected that electrical characteristics can be improved by using SiGe channel and source for n-channel as well as p-channel operation. In addition, ambipolar current that is caused by band-to-band tunneling (BTBT) between channel and drain can be suppressed by using elevated Si drain region. For obtaining fundamental electrical properties of tunnel FET with SiGe body, planar structures are firstly fabricated and analyzed with Si tunnel FET. From electrical characteristics of fabricated devices, it is observed that both n-type and p-type SiGe tunnel FETs have better switching properties than Si devices. Current saturations become faster and drive current shows 10 times more than that of Si tunnel FETs. In addition, BTBT model parameters of Si and Ge materials in fabricated devices are extracted through TCAD simulation. Extracted A and B parameters of BTBT model in Si are 4×1014 cm-1s-1 and 9.9×106 V/cm. Also, A and B parameters of Ge can be extracted as 3.1×1016 cm-1s-1 and 7.1×105 V/cm, respectively. Using calibrated model parameters, proposed tunnel FET is simulated and optimized in terms of switching properties with changing Ge contents, effect of the elevated Si drain region, short-channel effects, inverter operation, and device delay. Based on these optimized simulation results, the proposed tunnel FET is fabricated using spacer technique because it is possible to make self-aligned doping process. Key unit process is as follows: epitaxial growth for Si and SiGe materials, e-beam lithography for active-fin formation, and sidewall spacer gate formation. For n-channel and p-channel operation, fabricated tunnel FET shows the better electrical characteristics than control groups. Extracted point SS is 51.1 mV/dec for p-type tunnel FET and 87 mV/dec for n-type tunnel FET. Ambipolar current of the proposed tunnel FET is suppressed to 1/100 of that of planar SiGe tunnel FET. Also, in order to analyze current flow mechanism of tunnel FET, the electrical characteristics are measured with temperature variation. As temperature goes up, Shockley-Read-Hall and field-dependent generation are increased resulting in degradation of switching property. In current saturation region, BTBT which has low temperature sensitivity is dominant on current property. From this study, it is demonstrated that the novel tunnel FET with SiGe body and the elevated Si drain shows improved electrical performance compared with Si tunnel FET. Also, both n-type and p-type devices can obtain high current drivability and small SS without structure changes. This means that the proposed device has strong advantage in terms of implementing IC with tunnel FET. Thus, it will be one of the promising candidates for next-generation devices.Abstract i Contents iv List of Figures vi Chapter 1 1 Introduction 1 1.1 POWER ISSUES ON CMOS TECHNOLOGIES 1 1.2 TUNNEL FIELD-EFFECT TRANSISTOR (TUNNEL FET) 3 1.3 ISSUES IN TUNNEL FET 6 1.4 SCOPE OF THESIS 9 Chapter 2 11 Planar Si and SiGe tunnel FETs 11 2.1 EXPITAXY GROWTH FOR SI AND SIGE LAYERS 11 2.2 SIGE MOSCAP AND MOSFET FABRICATION 14 2.3 PLANAR SI AND SIGE TUNNEL FET 15 2.4 SUMMARY 34 Chapter 3 35 Device Simulation 35 3.1 PROPOSED TUNNEL FET 35 3.2 SIMULATION PARAMETERS AND RESULTS 37 3.3 TRANSIENT RESPONSE CHARACTERISTICS 43 Chapter 4 51 Device Characteristics 51 4.1 PROCESS FLOW 51 4.2 ACTIVE FIN PATTERNING USING E-BEAM LITHOGRAPHY 54 4.3 DRAIN AND GATE FORMATION 56 4.4 DEVICE CHARACTERISTICS 61 4.5 REASON OF DEGRADED CHARACTERISTICS IN N-TYPE DEVICE 70 Chapter 5 73 Conclusions 73 Bibliography 77 초록 78Docto

    Compact DC Modeling of Tunnel-FETs

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    En l'última dècada, el transistor d'efecte de camp amb efecte túnel (TFET) ha guanyat molt interès i es maneja com un possible successor de la tecnologia MOSFET convencional. El transport de càrrega en un TFET es basa en el mecanisme de túnel de banda a banda (B2B) i, per tant, el pendent sub-llindar a temperatura ambient pot superar el límit de 60 mV / dec. Per descriure i analitzar el comportament del TFET en les simulacions de circuits, aquesta dissertació introdueix un model compacte de CC per TFET de doble comporta. L'enfocament de modelatge considera l'efecte túnel B2B amb l'efecte parasitari del corrent túnel assistida per trampes (TAT) en l'estat ON i ambipolar del TFET. Inclou un paquet d'equacions compactes per al potencial 2D per descriure el diagrama de banda del TFET. Basat en el diagrama de banda, el B2B i el corrent TAT es deriven per separat. Per fer-ho, primer es troba una expressió compacta per la llargada túnel, que després s'utilitza juntament amb un enfocament numèric robust de tipus Wentzel-Kramers-Brillouin (WKB) per calcular la probabilitat túnel. Després, usant l'equació de túnel de Landauer, la taxa de generació túnel es calcula i s'aproxima per arribar a una expressió de forma tancada per a la densitat de corrent. Amb una aproximació addicional de la densitat de corrent utilitzant una funció matemàtica, s'aconsegueixen expressions compactes per al túnel B2B resultant i el corrent TAT. La verificació del model es realitza amb l'ajuda de les dades de simulació TCAD Sentaurus per diverses configuracions de simulació. A més, la validesa del model es demostra mitjançant mesuraments de TFET complementaris fabricats. Per demostrar l'estabilitat numèrica i la continuïtat, així com la flexibilitat, es realitzen i analitzen simulacions de circuits lògics basats en TFET com un inversor d'una sola etapa o una cel·la SRAM. La combinació del model CC amb un model TFET AC permet una simulació transitòria d'un oscil·lador en anell de 11 etapes.En la última década, el transistor de efecto de campo con efecto túnel (TFET) ha ganado mucho interés y se maneja como un posible sucesor de la tecnología MOSFET convencional. El transporte de carga en un TFET se basa en el mecanismo de túnel de banda a banda (B2B) y, por lo tanto, la pendiente sub-umbral a temperatura ambiente puede superar el límite de 60 mV / dec. Para describir y analizar el comportamiento del TFET en las simulaciones de circuitos, esta disertación introduce un modelo compacto de CC para TFET de doble compuerta. El enfoque de modelado considera el efecto túnel B2B con el efecto parasitario de la corriente túnel asistida por trampas (TAT) en el estado ON y AMBIPOLAR del TFET. Incluye un paquete de ecuaciones compactas del potencial 2D para describir el diagrama de banda del TFET. Basado en el diagrama de banda, el B2B y la corriente TAT se derivan por separado. Para hacerlo, primero se encuentra una expresión compacta para la longitud túnel, que luego se utiliza junto con un enfoque numérico robusto de tipo Wentzel-Kramers-Brillouin (WKB) para calcular la probabilidad túnel. Luego, usando la ecuación de túnel de Landauer, la tasa de generación túnel se calcula y aproxima para llegar a una expresión de forma cerrada para la densidad de corriente. Con una aproximación adicional de la densidad de corriente por una función matemática, se logran expresiones compactas para el túnel B2B resultante y la corriente TAT. La verificación del modelo se realiza con la ayuda de los datos de simulación TCAD Sentaurus para varias configuraciones de simulación. Además, la validez del modelo se demuestra mediante mediciones de TFET complementarios fabricados. Para demostrar la estabilidad numérica y la continuidad, así como la flexibilidad, se realizan y analizan simulaciones de circuitos lógicos basados en TFET como un inversor de una sola etapa o una celda SRAM. La combinación del modelo CC con un modelo TFET AC permite una simulación transitoria de un oscilador en anillo de 11 etapas.In the last decade, the tunnel field-effect transistor (TFET) has gained a lot of interest and is handled as a possible successor of the conventional MOSFET technology. The current transport of a TFET is based on the band-to-band (B2B) tunneling mechanism and therefore, the subthreshold slope at room temperature can overcome the limit of 60 mV/dec. In order to describe and analyze the TFET behavior in circuit simulations, this dissertation introduces a compact DC model for double-gate TFETs. The modeling approach considers the B2B tunneling and the parasitic effect of trap-assisted tunneling (TAT) in the ON- and AMBIPOLAR-state of the TFET. It includes a 2D compact potential equation package to de-scribe the band diagram of the TFET. Based on the band diagram, the B2B tunneling and TAT current part are derived separately. In order to do so, firstly a compact expression for the tunneling length is found, which is then used together with a numerical robust Wentzel-Kramers-Brillouin (WKB) approach to calculate the tunneling probability. Afterwards, using Landauer’s tunneling equation, the tunneling generation rate is calculated and approximated to come to a closed-form expression for the current density. Further approximation of the current density by a mathematical function, compact expressions for the resulting B2B tun-neling and TAT current are achieved. The verification of the model is done with the help of TCAD Sentaurus simulation data for various simulation setups. Furthermore, the validity of the model is proven by measurements of fabricated complementary TFETs. In order to demonstrate the numerical stability and continuity as well as the flexibility, simulations of TFET-based logic circuits like a single-stage inverter or an SRAM cell are performed and analyzed. The combination of the DC model with an TFET AC model allows for a transient simulation of an 11-stage ring oscillator

    높은 전류 구동능력을 가지는 SiGe 나노시트 구조의 터널링 전계효과 트랜지스터

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    학위논문 (박사) -- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2021. 2. 박병국.The development of very-large-scale integration (VLSI) technology has continuously demanded smaller devices to achieve high integration density for faster computing speed or higher capacity. However, in the recent complementary-metal-oxide-semiconductor (CMOS) technology, simple downsizing the dimension of metal-oxide-semiconductor field-effect transistor (MOSFET) no longer guarantees the boosting performance of IC chips. In particular, static power consumption is not reduced while device size is decreasing because voltage scaling is slowed down at some point. The increased off-current due to short-channel effect (SCE) of MOSFET is a representative cause of the difficulty in voltage scaling. To overcome these fundamental limits of MOSFET, many researchers have been looking for the next generation of FET device over the last ten years. Tunnel field-effect transistor (TFET) has been intensively studied for its steep switching characteristics. Nevertheless, the poor current drivability of TFET is the most serious obstacle to become competitive device for MOSFET. In this thesis, TFET with high current drivability in which above-mentioned problem is significantly solved is proposed. Vertically-stacked SiGe nanosheet channels are used to boost carrier injection and gate control. The fabrication technique to form highly-condensed SiGe nanosheets is introduced. TFET is fabricated with MOSFET with the same structure in the CMOS-compatible process. Both technology-computer-aided-design (TCAD) simulation and experimental results are utilized to support and examine the advantages of proposed TFET. From the perspective of the single device, the improvement in switching characteristics and current drivability are quantitatively and qualitatively analyzed. In addition, the device performance is compared to the benchmark of previously reported TFET and co-fabricated MOSFET. Through those processes, the feasibility of SiGe nanosheet TFET is verified. It is revealed that the proposed SiGe nanosheet TFET has notable steeper switching and low leakage in the low drive voltage as an alternative to conventional MOSFET.초고밀도 집적회로 기술의 발전은 고집적도 달성을 통해 단위 칩의 연산 속도 및 용량 향상에 기여할 소형의 소자를 끊임없이 요구하고 있다. 하지만 최신의 상보형 금속-산화막-반도체 (CMOS) 기술에서 금속-산화막-반도체 전계 효과 트랜지스터 (MOSFET) 의 단순한 소형화는 더 이상 집적회로의 성능 향상을 보장해 주지 못하고 있다. 특히 소자의 크기가 줄어드는 반면 정적 전력 소모량은 전압 스케일링의 둔화로 인해 감소되지 않고 있는 상황이다. MOSFET의 짧은 채널 효과로 인해 증가된 누설 전류가 전압 스케일링의 어려움을 주는 대표적 원인으로 꼽힌다. 이러한 근본적인 MOSFET의 한계를 극복하기 위하여 지난 10여년간 새로운 단계의 전계 효과 트랜지스터 소자들이 연구되고 있다. 그 중 터널 전계 효과 트랜지스터(TFET)은 그 특유의 우수한 전원 특성으로 각광받아 집중적으로 연구되고 있다. 많은 연구에도 불구하고, TFET의 부족한 전류 구동 능력은 MOSFET의 대체재로 자리매김하는 데 가장 큰 문제점이 되고 있다. 본 학위논문에서는 상기된 문제점을 해결할 수 있는 우수한 전류 구동 능력을 가진 TFET이 제안되었다. 반송자 유입과 게이트 컨트롤을 향상시킬 수 있는 수직 적층된 실리콘저마늄(SiGe) 나노시트 채널이 사용되었다. 또한, 제안된 TFET은 CMOS 기반 공정을 활용하여 MOSFET과 함께 제작되었다. 테크놀로지 컴퓨터 지원 설계(TCAD) 시뮬레이션과 실제 측정 결과를 활용하여 제안된 소자의 우수성을 검증하였다. 단위 CMOS 소자의 관점에서, 전원 특성과 전류 구동 능력의 향상을 정량적, 정성적 방법으로 분석하였다. 그리고, 제작된 소자의 성능을 기존 제작 및 보고된 TFET 및 함께 제작된 MOSSFET과 비교하였다. 이러한 과정을 통해, 실리콘저마늄 나노시트 TFET의 활용 가능성이 입증되었다. 제안된 실리콘저마늄 나노시트 소자는 주목할 만한 전원 특성을 가졌고 저전압 구동 환경에서 한층 더 낮은 누설 전류를 가짐으로써 향후 MOSFET을 대체할만한 충분한 가능성을 보여주었다.Chapter 1 Introduction 1 1.1. Power Crisis of Conventional CMOS Technology 1 1.2. Tunnel Field-Effect Transistor (TFET) 6 1.3. Feasibility and Challenges of TFET 9 1.4. Scope of Thesis 11 Chapter 2 Device Characterization 13 2.1. SiGe Nanosheet TFET 13 2.2. Device Concept 15 2.3. Calibration Procedure for TCAD simulation 17 2.4. Device Verification with TCAD simulation 21 Chapter 3 Device Fabrication 31 3.1. Fabrication Process Flow 31 3.2. Key Processes for SiGe Nanosheet TFET 33 3.2.1. Key Process 1 : SiGe Nanosheet Formation 34 3.2.2. Key Process 2 : Source/Drain Implantation 41 3.2.3. Key Process 3 : High-κ/Metal gate Formation 43 Chapter 4 Results and Discussion 53 4.1. Measurement Results 53 4.2. Analysis of Device Characteristics 56 4.2.1. Improved Factors to Performance in SiGe Nanosheet TFET 56 4.2.2. Performance Comparison with SiGe Nanosheet MOSFET 62 4.3. Performance Evaluation through Benchmarks 64 4.4. Optimization Plan for SiGe nanosheet TFET 66 4.4.1. Improvement of Quality of Gate Dielectric 66 4.4.2. Optimization of Doping Junction at Source 67 Chapter 5 Conclusion 71 Bibliography 73 Abstract in Korean 81 List of Publications 83Docto

    높은 구동 전류와 낮은 문턱전압 이하 스윙을 가지는 L자 형태의 터널링 전계효과 트랜지스터

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    학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 박병국.In order to solve power crisis in highly-scaled CMOS technology, a novel tunnel field-effect transistors (TFETs), named L-shaped TFETs, have been proposed and its electrical properties are examined. It features band-to-band tunneling (BTBT) direction parallel to the normal electric field induced by gate electrode. Because carrier injection is occurred perpendicular to the channel direction, cross-sectional area and barrier width of BTBT junction could be defined by structural parameters. Using the commercial TCAD device simulator, its electrical characteristics are examined and optimized. It is expected that the L-shaped TFETs will reveal better performance than conventional ones in terms of subthreshold swing (S), on-current (Ion) and short channel effect. In addition, the performance of L-shaped TFET inverters has been compared with that of conventional TFET ones for its complementary logic application. After the key process techniques are obtained, control and comparison samples are fabricated at Inter-University Semiconductor Research Center (ISRC) of Seoul National University (SNU), Korea. The main process technique is as follow: in-situ doped epitaxial layer growth for constantly doped source region, selective epitaxial layer growth of silicon at low temperature for tunneling region, and guarantee sub-3-nm gate dielectric. From the electrical measurement of transfer and output characteristics, it is verified that 102 mV/dec minimum S in conventional TFET is improve to 7, 34 and 59 mV/dec in L-shaped TFET. In addition, the Ion of L-shaped TFET is more than 10 times larger than that of conventional one. Extracting several parameters such as source/drain resistance, channel resistance, mobility, and tunneling resistance, it is clear that the improved performance comes from the reduction of tunneling resistance. From this study, it is demonstrated that L-shaped TFET will be one of the most promising candidate for a next-generation low-power device.Abstract i Contents iii List of Tables v List of Figures vi Chapter 1 Introduction 1 1.1 NECESSITY OF ALTERNATIVES TO CMOS 1 1.2 TUNNEL FIELD-EFFECT TRANSISTORS (TFETS) 4 1.3 TECHNICAL ISSUES OF TFETS 7 1.4 SCOPE OF THESIS 10 Chapter 2 L-shaped TFET 11 2.1 FEATURES OF L-SHAPED TFET 11 2.2 DESIGN OPTIMIZATION 17 2.3 CORNER EFFECT 27 2.4 FURTHER IMPROVEMENT AND CIRCUIT APPLICATION 36 2.5 SUMMARY OF TARGET DEVICE 40 Chapter 3 Device Fabrication 42 3.1 FABRICATION OF CONTROL TFETS 42 3.2 KEY PROCESS DESIGNS FOR L-SHAPED TFETS 45 3.3 FABRICATION OF L-SHAPED TFET 51 3.4 SIDEWALL SPACER FOR MINIMIZATION OF MIS-ALIGNMENT 56 Chapter 4 Device Characteristics 59 4.1 METAL-OXIDE-SEMICONDUCTOR (MOS) CAPACITOR 59 4.2 CONTROL SAMPLES OF CONVENTIONAL PLANAR TFETS 63 4.3 L-SHAPED TFETS 71 4.4 EXTRACTION OF SEVERAL ELECTRICAL PARAMETERS 76 Chapter 5 80 Conclusions 80 Bibliography 82 Abstract in Korean 89 Curriculum Vitae 91Docto

    Charge Transport in 2D MoS2, WS2, and MoS2–WS2 Heterojunction-Based Field-Effect Transistors: Role of Ambipolarity

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    Electrical and optical characteristics of few-layered (3–4 L) chemical vapor deposition (CVD) grown MoS2, WS2, and MoS2–WS2 heterostructure-based back-gated field-effect transistor (FET) devices have herein been studied. The structure, stoichiometry, and work function of the two-dimensional (2D) materials that comprise the channel region have been comprehensively characterized. The MoS2 device exhibits a unipolar n-type behavior with a high field-effect ON/OFF ratio (>103) and a low subthreshold swing of 668 mV/decade at room temperature. WS2 and MoS2–WS2 heterostructure devices exhibit gate driven ambipolarity due to chemically active defect sites, offering precise control on the carrier type necessary for realization of logic devices. Record-high room-temperature electron mobility (19 cm2/V.s) exhibited by the MoS2–WS2 heterostructure device displays an improved electrical performance of almost one order of magnitude higher than already existing 2D devices. The prototype of a 2D complementary metal–oxide–semiconductor (CMOS) logic inverter switch integrating high electronic and optical responses of the MoS2–WS2 heterostructure junction owing to ambipolar FET operation has been demonstrated. The achieved results encompassing superior photoabsorption, atomically thin thickness, and high performance indices suggest that soft 2D heterostructure devices may open a new paradigm in artificial retinal implants and photoelectronics.acceptedVersio

    Miniaturized Transistors

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    What is the future of CMOS? Sustaining increased transistor densities along the path of Moore's Law has become increasingly challenging with limited power budgets, interconnect bandwidths, and fabrication capabilities. In the last decade alone, transistors have undergone significant design makeovers; from planar transistors of ten years ago, technological advancements have accelerated to today's FinFETs, which hardly resemble their bulky ancestors. FinFETs could potentially take us to the 5-nm node, but what comes after it? From gate-all-around devices to single electron transistors and two-dimensional semiconductors, a torrent of research is being carried out in order to design the next transistor generation, engineer the optimal materials, improve the fabrication technology, and properly model future devices. We invite insight from investigators and scientists in the field to showcase their work in this Special Issue with research papers, short communications, and review articles that focus on trends in micro- and nanotechnology from fundamental research to applications

    저전력 동작을 위하여 채널에 직각인 터널방향과 수직형 구조를 가지는 터널 전계효과 트랜지스터

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    학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 박병국.In this work, Tunnel Field-Effect Transistors (TFETs) with a novel structure will be proposed as a substituting devices which can implement steeper switching than the conventional MOSFETs do in low power operation. It is experimentally demonstrated that applying a vertical structure with a perpendicular tunnel to the channel can achieve an operation of high electrical performance and it can be integrated in a bulk Si substrate. First of all, Si and SiGe TFETs with a planar structure are fabricated and measured to extract model parameters. From the measured results, the parameters of band-to-band tunnel (BTBT) model, which can be used to simulate TFETs accurate are calibrated. In this regard, Synopsys Sentaurus Device will be used for this purpose. Then, based on the simulation of planar TFETs, the proposed devices will be presented as the vertical TFETs with the perpendicular tunnel junction based on the bulk Si substrate. The perpendicular tunnel junction and the large tunnel area are employed on the source side to achieve a steep subthreshold swing (SS) and high ON-current (ION), which can lead to TFETs outstanding performance. Moreover, the ION can be increased easily by adjusting a height of overlap region between a source and a gate. Although, the TFETs show good electrical performance, there is a hump phenomenon in transfer curve. In order to suppress the hump phenomenon in the transfer curves, the hump behavior in the proposed device should be investigated. After investigating it, the hump behavior is found to be originated from the two different tunnel regions. Moreover their threshold voltages originated from different tunnel show different values. In order to improve the electrical performance, a capping layer which can be made by gradual doping is inserted on the source. Then, the hump behavior can be expected to decrease. Finally, the proposed TFETs will be fabricated on the bulk Si substrate. A thin intrinsic Si is epitaxially grown on the source region which forms the perpendicular tunnel junction to the channel, resulting in abrupt band bending. The fabricated the proposed TFETs show 17 mV/dec minimum subthreshold swing (SS) and 104 ON/OFF current ratio (ION/IOFF ) for sub-0.7 V gate overdrive. In addition, SS is maintained less than 60 mV/dec while a drain current increases from complete OFF-state (10−13) to more than two orders of magnitude (10−11). In conclusion, the proposed device are fabricated successfully. From this study, it is demonstrated that the proposed TFETs will be one of the most promising candidate for a next-generation low-power device.Chapter 1 Introduction 1 1.1 Power issues on CMOS technologies 1 1.2 Tunnel Field Effect Transistors 3 1.3 Issue for TFETs 6 1.4 Propose of the Target Device 8 1.5 Thesis outline 10 Chapter 2 Planar Si & SiGe TFET 12 2.1 Device fabrication 12 2.2 Measured Results 14 2.3 BTBT model calibrations 17 2.4 Summary 19 2.5 Appendix: Process Flow 19 Chapter 3 Simulation of the Proposed TFETs 24 3.1 Introduction 25 3.2 Device structure and Fabrication Method 25 3.3 Simulation Results and Discussion 27 3.4 Summary of Simulation 34 Chapter 4 Fabrication of the Proposed TFETs 36 4.1 Introduction 37 4.2 Device Structure and Fabrication Method 37 4.3 Experimental results 47 4.4 Discussion 52 4.4.1 High OFF leakage current 52 4.4.2 Short channel effect 54 4.4.3 Current Saturation by Drain 56 4.4.4 Process Optimization 59 4.5 Summary 61 4.6 Appendix: Process Flow 61 Chapter 5 Conclusion 68 5.1 Summary of Contributions 68 5.2 Future works for TFETs Design 69 Chapter 6 Appendix 71 6.1 Super-linear onset in TFETs 71 6.2 Introduction 72 6.3 Device Structure 72 6.4 Simulation Results 73 6.5 Drain Threshold Voltage 79 6.6 Tunnel Resistance 80 6.7 Conclusion 86 Bibliography 88 초록 95Docto
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