Maximizing Crosstalk-Induced Slowdown During Path Delay Test

Capacitive crosstalk between adjacent signal wires in integrated circuits may lead to noise or a speedup or slowdown in signal transitions. These in turn may lead to circuit failure or reduced operating speed. This thesis focuses on generating test patterns to induce crosstalk-induced signal delays, in order to determine whether the circuit can still meet its timing specification. A timing-driven test generator is developed to sensitize multiple aligned aggressors coupled to a delay-sensitive victim path to detect the combination of a delay spot defect and crosstalk-induced slowdown. The framework uses parasitic capacitance information, timing windows and crosstalk-induced delay estimates to screen out unaligned or ineffective aggressors coupled to a victim path, speeding up crosstalk pattern generation. In order to induce maximum crosstalk slowdown along a path, aggressors are prioritized based on their potential delay increase and timing alignment. The test generation engine introduces the concept of alignment-driven path sensitization to generate paths from inputs to coupled aggressor nets that meet timing alignment and direction requirements. By using path delay information obtained from circuit preprocessing, preferred paths can be chosen during aggressor path propagation processes. As the test generator sensitizes aggressors in the presence of victim path necessary assignments, the search space is effectively reduced for aggressor path generation. This helps in reducing the test generation time for aligned aggressors. In addition, two new crosstalk-driven dynamic test compaction algorithms are developed to control the increase in test pattern count. The proposed test generation algorithm is applied to ISCAS85 and ISCAS89 benchmark circuits. SPICE simulation results demonstrate the ability of the alignment-driven test generator to increase crosstalk-induced delays along victim paths

Towards all-optical label switching nodes with multicast

Fiber optics has developed so rapidly during the last decades that it has be- come the backbone of our communication systems. Evolved from initially static single-channel point-to-point links, the current advanced optical backbone net- work consists mostly of wavelength-division multiplexed (WDM) networks with optical add/drop multiplexing nodes and optical cross-connects that can switch data in the optical domain. However, the commercially implemented optical net- work nodes are still performing optical circuit switching using wavelength routing. The dedicated use of wavelength and infrequent recon¯guration result in relatively poor bandwidth utilization. The success of electronic packet switching has inspired researchers to improve the °exibility, e±ciency, granularity and network utiliza- tion of optical networks by introducing optical packet switching using short, local optical labels for forwarding decision making at intermediate optical core network nodes, a technique that is referred to as optical label switching (OLS). Various research demonstrations on OLS systems have been reported with transparent optical packet payload forwarding based on electronic packet label processing, taking advantage of the mature technologies of electronic logical cir- cuitry. This approach requires optic-electronic-optic (OEO) conversion of the op- tical labels, a costly and power consuming procedure particularly for high-speed labels. As optical packet payload bit rate increases from gigabit per second (Gb/s) to terabit per second (Tb/s) or higher, the increased speed of the optical labels will eventually face the electronic bottleneck, so that the OEO conversion and the electronic label processing will be no longer e±cient. OLS with label processing in the optical domain, namely, all-optical label switching (AOLS), will become necessary. Di®erent AOLS techniques have been proposed in the last ¯ve years. In this thesis, AOLS node architectures based on optical time-serial label processing are presented for WDM optical packets. The unicast node architecture, where each optical packet is to be sent to only one output port of the node, has been in- vestigated and partially demonstrated in the EU IST-LASAGNE project. This thesis contributes to the multicast aspects of the AOLS nodes, where the optical packets can be forwarded to multiple or all output ports of a node. Multicast capable AOLS nodes are becoming increasingly interesting due to the exponen- tial growth of the emerging multicast Internet and modern data services such as video streaming, high de¯nition TV, multi-party online games, and enterprise ap- plications such as video conferencing and optical storage area networks. Current electronic routers implement multicast in the Internet protocol (IP) layer, which requires not only the OEO conversion of the optical packets, but also exhaus- tive routing table lookup of the globally unique IP addresses. Despite that, there has been no extensive studies on AOLS multicast nodes, technologies and tra±c performance, apart from a few proof-of-principle experimental demonstrations. In this thesis, three aspects of the multicast capable AOLS nodes are addressed: 1. Logical design of the AOLS multicast node architectures, as well as func- tional subsystems and interconnections, based on state-of-the-art literature research of the ¯eld and the subject. 2. Computer simulations of the tra±c performance of di®erent AOLS unicast and multicast node architectures, using a custom-developed AOLS simulator AOLSim. 3. Experimental demonstrations in laboratory and computer simulations using the commercially available simulator VPItransmissionMakerTM, to evaluate the physical layer performance of the required all-optical multicast technolo- gies. A few selected multi-wavelength conversion (MWC) techniques are particularly looked into. MWC is an essential subsystem of the AOLS node for realizing optical packet multicast by making multiple copies of the optical packet all-optically onto di®er- ent wavelengths channels. In this thesis, theMWC techniques based on cross-phase modulation and four-wave mixing are extensively investigated. The former tech- nique o®ers more wavelength °exibility and good conversion e±ciency, but it is only applicable to intensity modulated signals. The latter technique, on the other hand, o®ers strict transparency in data rate and modulation format, but its work- ing wavelengths are limited by the device or component used, and the conversion e±ciency is considerably lower. The proposals and results presented in this thesis show feasibility of all-optical packet switching and multicasting at line speed without any OEO conversion and electronic processing. The scalability and the costly optical components of the AOLS nodes have been so far two of the major obstacles for commercialization of the AOLS concept. This thesis also introduced a novel, scalable optical labeling concept and a label processing scheme for the AOLS multicast nodes. The pro- posed scheme makes use of the spatial positions of each label bit instead of the total absolute value of all the label bits. Thus for an n-bit label, the complexity of the label processor is determined by n instead of 2n

Photonic logic-gates: boosting all-optical header processing in future packet-switched networks

Las redes ópticas de paquetes se han convertido en los últimos años en uno de los temas de vanguardia en el campo de las tecnologías de comunicaciones. El procesado de cabeceras es una de las funciones más importantes que se llevan a cabo en nodos intermedios, donde un paquete debe ser encaminado a su destino correspondiente. El uso de tecnología completamente óptica para las funciones de encaminamiento y reconocimiento de cabeceras reduce el retardo de procesado respecto al procesado eléctrico, disminuyendo de ese modo la latencia en el enlace de comunicaciones. Existen diferentes métodos de procesado de datos para implementar el reconocimiento de cabeceras. El objetivo de este trabajo es la propuesta de una nueva arquitectura para el procesado de cabeceras basado en el uso de puertas lógicas completamente ópticas. Estas arquitecturas tienen como elemento clave el interferómetro Mach-Zehnder basado en el amplificador óptico de semiconductor (SOA-MZI), y utilizan el efecto no lineal de modulación cruzada de fase (XPM) en los SOAs para realizar dicha funcionalidad. La estructura SOA-MZI con XPM es una de las alternativas más atractivas debido a las numerosas ventajas que presenta, como por ejemplo los requisitos de baja energía para las señales de entrada, su diseño compacto, una elevada relación de extinción (ER), regeneración de la señal y el bajo nivel de chirp que introducen. Este trabajo se ha centrado en la implementación de la funcionalidad lógica XOR. Mediante esta función se pueden realizar diversas funcionalidades en las redes ópticas. Se proponen dos esquemas para el reconocimiento de cabeceras basados en el uso de la puerta XOR. El primer esquema utiliza puertas en cascada. El segundo esquema presenta una arquitectura muy escalable, y se basa en el uso de un bucle de realimentación implementado a la salida de la puerta. Asimismo, también se presentan algunas aplicaciones del procesado de cabeceras para el encaminamiento de paquetes basadas en el uso dMartínez Canet, JM. (2006). Photonic logic-gates: boosting all-optical header processing in future packet-switched networks [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/1874Palanci

Architectural Exploration and Design Methodologies of Photonic Interconnection Networks

Photonic technology is becoming an increasingly attractive solution to the problems facing today's electronic chip-scale interconnection networks. Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely high-bandwidth density and energy-efficient links for on- and off-chip communications. From the feasibility and architecture perspective however, photonics represents a dramatic paradigm shift from traditional electronic network designs due to fundamental differences in how electronics and photonics function and behave. As a result of these differences, new modeling and analysis methods must be employed in order to properly realize a functional photonic chip-scale interconnect design. In this work, we present a methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures. We also describe a set of tools which can be utilized to assess the physical-layer and system-level performance properties of a photonic network. The models and tools are integrated in a novel open-source design and simulation environment called PhoenixSim. Next, we leverage PhoenixSim for the study of chip-scale photonic networks. We examine several photonic networks through the synergistic study of both physical-layer metrics and system-level metrics. This holistic analysis method enables us to provide deeper insight into architecture scalability since it considers insertion loss, crosstalk, and power dissipation. In addition to these novel physical-layer metrics, traditional system-level metrics of bandwidth and latency are also obtained. Lastly, we propose a novel routing architecture known as wavelength-selective spatial routing. This routing architecture is analogous to electronic virtual channels since it enables the transmission of multiple logical optical channels through a single physical plane (i.e. the waveguides). The available wavelength channels are partitioned into separate groups, and each group is routed independently in the network. Each partition is spectrally multiplexed, as opposed to temporally multiplexed in the electronic case. The wavelength-selective spatial routing technique benefits network designers by provider lower contention and increased path diversity

Label-controlled optical switching nodes

Optical networks are evolving from initially static optical circuits and subsequently optical circuit switching towards optical packet switching in order to take advan- tage of the high transport capacity made available by WDM systems in a more °exible and e±cient way. Optically labeling of packets and routing the packets's payload optically under control of its label allows the network nodes to route and forward IP data without having to process the payload, thus keeping it in the optical domain; this is a promising solution to avoid electronic bottlenecks in routers. All-optical label switching can therefore be used to route and forward packets independent of their length and payload bitrate. Several optical signal labeling techniques have been proposed in previous re- search reported in literature; orthogonal labeling and time-serial labeling have been studied in this thesis. This thesis studies two orthogonal modulation label- ing techniques: one based on FSK labels with an IM payload, and another one on SCM labeling for a DPSK modulated payload. A time-serial labeling method based on IM labels with IM or DPSK payload is also presented and studied. The ¯rst two techniques assume electronic processing of the labels in the node, and hence assume that labels can be transmitted at a much lower bitrate than the payload data rate. The third technique assumes all-optical signal processing in the nodes, capable of handling a label at the same bitrate or slightly lower than the payload data. Labels at low bitrate in comparison with the payload bitrate are desirable in systems where the label processing will be conducted in the electrical domain, while labels at the same bitrate as the payload can be used in systems where the processing is conducted in the optical domain, exploiting all-optical processing techniques. These three techniques have been chosen because they are compatible with the existing networks, since the modulation format, bitrates, transmission properties, and other features of the signals are similar to the ones used for commercially available applications. Thus, they can be considered important candidates for migration scenarios from optical circuit switching towards optical burst switching networking. Orthogonal labeling based on FSK/IM is a promising scheme for implementing the labeling of optical signals, and it is the technology of choice in the STOLAS project. This technique o®ers advantageous features such as a relaxed timing de- lineation between payload and label, and ease of label erasure and re-writing of new labels. By using wavelength-agile tunable laser sources with FSK modula- tion capability, wavelength converters, and passive wavelength routing elements, a scalable modular label-controlled router featuring high reliability can be built. In this thesis, several aspects of the physical parameters of an FSK/IM labeling scheme within a routing node have been studied and presented. Optical ¯ltering requires special care, since the combined FSK/IM scheme has a broader spectrum than that of pure intensity modulated signals. The requirements on the limited extinction ratio for the IM signal can be relaxed at low bitrates of the label signal or, alternatively, by introducing data encoding. Optical labeling by using FSK/IM represents a simple and attractive way of implementing hybrid optical circuit and burst switching in optical networks. Architecturally, similar advantages can be mentioned for the second orthogo- nal labeling technique studied in this thesis, based on SCM labels and a DPSK payload. In-band subcarriers carrying low bitrate labels located at a frequency equal to half the bitrate of the payload signal can be inserted introducing only low power penalties. Wavelength conversion can be implemented by using passive highly nonlinear ¯bers and exploiting the four-wave mixing e®ect. This thesis also studies the design of two functional blocks of an all-optical core node proposed in the LASAGNE project, namely the all-optical label and payload separator and the wavelength converter unit for a time-serial labeling scheme. The label and payload processor can be realized exploiting nonlinear e®ects in SOAs. An implementation using polarization division multiplexing to transport the external control light for an IM/IM time-serial scheme was demon- strated. Label and payload processors with self-contained control signals were also demonstrated, either using a DPSK signal to simultaneously transport the payload data and the control signal or inserting a CW dummy in between the label and the payload, which were based on IM-RZ format. A study on single- and multi- wavelength conversion based on FWM in a HNLF was presented. This approach allows transparent wavelength conversion (independent of the data format used) at high bitrates (the nonlinear e®ects in a ¯ber are obtained at ultrafast speeds). The labeling techniques explored have indicated a viable way of migration towards optical burst packet switched networks while signi¯cantly improving the throughput of the routing nodes

Investigating the Optical Link Performance of the End-of Substructure Card and Susceptibility to SEUs

Particle physics experiments carried out by CERN attempt to investigate the fundamental forces of matter. One of these experiments is the ATLAS experiment, which studies the proton-proton collisions in the LHC. A series of upgrades are planned to increase the luminosity by a factor of five, leading to the high-luminosity LHC (HL-LHC). This upgrade will increase the potential for new discoveries but brings with it design challenges in relation to the harsh radiation environment and significant data throughput required. The ATLAS experiment is building a new detector to cope with these challenges, titled the Inner Tracker (ITk). A crucial part of this new detector is the End-of-Substructure (EoS) card, which constitutes the interface between the ondetector electronics and the off-detector systems. In addition to the operational challenges, the HL-LHC does not allow for repairs or replacing of EoS cards once operation commences, emphasizing the need for thorough testing and qualification of this component. This thesis focuses on characterizing the performance of the EoS card in the presence of radiation, under non-ideal operating conditions and the impact of optical link parameters. The first set of tests is centered on qualifying the radiation tolerance of the EoS card. The radiation environment within the ITk poses a threat to the stable operation of electronics as energetic particles have the potential to cause erroneous changes in device logic, known as Single Event Upsets (SEU). The SEU susceptibility of the EoS card, with a focus on the Versatile Link Plus Transceiver (VTRx+) component, is studied by irradiating the EoS card with a neutron source with a distributed energy spectrum and a peak energy of 11MeV while performing a bit error rate (BER) test to monitor for radiation induced errors. The second set of tests deals with characterizing the impact of an irregular power supply on the EoS card's performance through simulating noise on the supply lines and monitoring the response in BER. The final set of tests investigates the impact the VTRx+ configuration parameters have on the quality of the optical signal. These tests were carried out at the University of Cape Town (UCT) with the support of DESY, a national research institute in Germany, responsible for the production of the EoS cards. A number of new firmware, software and hardware modules were developed as part of this work in order to carry out the tests required. The most significant of which comprised a novel firmware addition allowing for the evaluation of the optical signal quality with an FPGA. This contribution is now being integrated into the quality control proceedings at DESY, to be used in assessing optical signal quality of the entire set of approximately 1552 EoS cards being produced