1,164 research outputs found

    Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks

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    While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements

    Power management techniques in an FPGA-Based WSN node for high performance application

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    In this work, the power management techniques implemented in a high-performance node for Wireless Sensor Networks (WSN) based on a RAM-based FPGA are presented. This new node custom architecture is intended for high-end WSN applications that include complex sensor management like video cameras, high compute demanding tasks such as image encoding or robust encryption, and/or higher data bandwidth needs. In the case of these complex processing tasks, yet maintaining low power design requirements, it can be shown that the combination of different techniques such as extensive HW algorithm mapping, smart management of power islands to selectively switch on and off components, smart and low-energy partial reconfiguration, an adequate set of save energy modes and wake up options, all combined, may yield energy results that may compete and improve energy usage of typical low power microcontrollers used in many WSN node architectures. Actually, results show that higher complexity tasks are in favor of HW based platforms, while the flexibility achieved by dynamic and partial reconfiguration techniques could be comparable to SW based solutions

    Using Partial Reconfiguration for SoC Design and Implementation

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    Most reconfigurable systems rely on FPGA technology. Among these ones, those which permit dynamic and partial reconfiguration, offer added benefits in flexibility, in-field device upgrade, improved design and manufacturing time, and even, in some cases, power consumption reductions. However, dynamic reconfiguration is a complex task, and the real benefits of its use in real applications have been often questioned. This paper presents an overview of the partial reconfiguration technique application, along with four original applications. The main goal of these applications is to test several architectures with different flexibility and, to search for the partial reconfiguration "killing application", that is, the application that better demonstrates the benefits of today reconfigurable systems based on commercial FPGAs. Therefore, the presented applications are rather a proof of concept, than fully operative and closed systems. First, a brief introduction to the partial reconfigurable systems application topic has been included. After that, the descriptions of the created reconfigurable systems are presented: first, an on-chip communications emulation framework, second, an on chip debugging system, third, a wireless sensor network reconfigurable node and finally, a remote reconfigurable client-server device. Each application is described in a separate section of the paper along with some test and results. General conclusions are included at the end of the pape

    Remote reconfiguration of FPGA-based wireless sensor nodes for flexible Internet of Things

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    Recently, sensor nodes in Wireless Sensor Networks (WSNs) have been using Field Programmable Gate Arrays (FPGA) for high-speed, low-power processing and reconfigurability. Reconfigurability enables adaptation of functionality and performance to changing requirements. This paper presents an efficient architecture for full remote reconfiguration of FPGA-based wireless sensors. The novelty of the work includes the ability to wirelessly upload new configuration bitstreams to remote sensor nodes using a protocol developed to provide full remote access to the flash memory of the sensor nodes. Results show that the FPGA can be remotely reconfigured in 1.35 s using a bitstream stored in the flash memory. The proposed scheme uses negligible amount of FPGA logic and does not require a dedicated microcontroller or softcore processor. It can help develop truly flexible IoT, where the FPGAs on thousands of sensor nodes can be reprogrammed or new configuration bitstreams uploaded without requiring physical access to the nodes. © 202

    FPGA-Based Wireless Sensor Node Architecture for High Performance Applications

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    While for years traditional wireless sensor nodes have been based on ultra-low power microcontrollers with sufficient but limited computing power, the complexity and number of tasks of today’s applications are constantly increasing. Increasing the node duty cycle is not feasible in all cases, so in many cases more computing power is required. This extra computing power may be achieved by either more powerful microcontrollers, though more power consumption or, in general, any solution capable of accelerating task execution. At this point, the use of hardware based, and in particular FPGA solutions, might appear as a candidate technology, since though power use is higher compared with lower power devices, execution time is reduced, so energy could be reduced overall. In order to demonstrate this, an innovative WSN node architecture is proposed. This architecture is based on a high performance high capacity state-of-the-art FPGA, which combines the advantages of the intrinsic acceleration provided by the parallelism of hardware devices, the use of partial reconfiguration capabilities, as well as a careful power-aware management system, to show that energy savings for certain higher-end applications can be achieved. Finally, comprehensive tests have been done to validate the platform in terms of performance and power consumption, to proof that better energy efficiency compared to processor based solutions can be achieved, for instance, when encryption is imposed by the application requirements

    Dynamic Reconfiguration in Camera Networks: A Short Survey

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    There is a clear trend in camera networks towards enhanced functionality and flexibility, and a fixed static deployment is typically not sufficient to fulfill these increased requirements. Dynamic network reconfiguration helps to optimize the network performance to the currently required specific tasks while considering the available resources. Although several reconfiguration methods have been recently proposed, e.g., for maximizing the global scene coverage or maximizing the image quality of specific targets, there is a lack of a general framework highlighting the key components shared by all these systems. In this paper we propose a reference framework for network reconfiguration and present a short survey of some of the most relevant state-of-the-art works in this field, showing how they can be reformulated in our framework. Finally we discuss the main open research challenges in camera network reconfiguration

    Recent Advances in Wireless Communications and Networks

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    This book focuses on the current hottest issues from the lowest layers to the upper layers of wireless communication networks and provides "real-time" research progress on these issues. The authors have made every effort to systematically organize the information on these topics to make it easily accessible to readers of any level. This book also maintains the balance between current research results and their theoretical support. In this book, a variety of novel techniques in wireless communications and networks are investigated. The authors attempt to present these topics in detail. Insightful and reader-friendly descriptions are presented to nourish readers of any level, from practicing and knowledgeable communication engineers to beginning or professional researchers. All interested readers can easily find noteworthy materials in much greater detail than in previous publications and in the references cited in these chapters

    Quality-of-Information Aware Sensing Node Characterisation for Optimised Energy Consumption in Visual Sensor Networks

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    Energy consumption is one of the primary concerns in a resource constrained visual sensor network (VSN) with wireless transceiving capability. The existing VSN design solutions under particular resource constrained scenarios are application-specific, whereas the degree of sensitivity of the resource constraints varies from one application to another. This limits the implementation of the existing energy efficient solutions within a VSN node, which may be considered to be a part of a heterogeneous network. This thesis aims to resolve the energy consumption issues faced within VSNs because of their resource constrained nature by proposing energy efficient solutions for sensing nodes characterisation. The heterogeneity of image capture and processing within a VSN can be adaptively reflected with a dynamic field-of-view (FoV) realisation. This is expected to allow the implementation of a generalised energy efficient solution that will adapt with the heterogeneity of the network. In this thesis, a FoV characterisation framework is proposed, which can assist design engineers during the pre-deployment phase in developing energy efficient VSNs. The proposed FoV characterisation framework provides efficient solutions for: 1) selecting suitable sensing range; 2) maximising spatial coverage; 3) minimising the number of required nodes; and 4) adaptive task classification. The task classification scheme proposed in this thesis exploits heterogeneity of the network and leads to an optimal distribution of tasks between visual sensing nodes. Soft decision criteria is exploited, and it is observed that for a given detection reliability, the proposed FoV characterisation framework provides energy efficient solutions which can be implemented within heterogeneous networks. In the post-deployment phase, the energy efficiency of a VSN for a given level of reliability can be enhanced by reconfiguring its nodes dynamically to achieve optimal configurations. Considering the dynamic realisation of quality-of-information (QoI), a strategy is devised for selecting suitable configurations of visual sensing nodes to reduce redundant visual content prior to transmission without sacrificing the expected information retrieval reliability. By incorporating QoI awareness using peak signal-to-noise ratio-based representative metric, the distributed nature of the proposed self-reconfiguration scheme accelerates the decision making process. This thesis also proposes a unified framework for node classification and dynamic self-reconfiguration in VSNs. For a given application, the unified framework provides a feasible solution to classify and reconfigure visual sensing nodes based on their FoV by exploiting the heterogeneity of targeted QoI within the sensing region. From the results, it is observed that for the second degree of heterogeneity in targeted QoI, the unified framework outperforms its existing counterparts and results in up to 72% energy savings with as low as 94% reliability. Within the context of resource constrained VSNs, the substantial energy savings achieved by the proposed unified framework can lead to network lifetime enhancement. Moreover, the reliability analysis demonstrates suitability of the unified framework for applications that need a desired level of QoI

    Department of Computer Science Activity 1998-2004

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    This report summarizes much of the research and teaching activity of the Department of Computer Science at Dartmouth College between late 1998 and late 2004. The material for this report was collected as part of the final report for NSF Institutional Infrastructure award EIA-9802068, which funded equipment and technical staff during that six-year period. This equipment and staff supported essentially all of the department\u27s research activity during that period
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