284 research outputs found

    Low-power CMOS front-ends for wireless personal area networks

    Get PDF
    The potential of implementing subthreshold radio frequency circuits in deep sub-micron CMOS technology was investigated for developing low-power front-ends for wireless personal area network (WPAN) applications. It was found that the higher transconductance to bias current ratio in weak inversion could be exploited in developing low-power wireless front-ends, if circuit techniques are employed to mitigate the higher device noise in subthreshold region. The first fully integrated subthreshold low noise amplifier was demonstrated in the GHz frequency range requiring only 260 ÎŒW of power consumption. Novel subthreshold variable gain stages and down-conversion mixers were developed. A 2.4 GHz receiver, consuming 540 ÎŒW of power, was implemented using a new subthreshold mixer by replacing the conventional active low noise amplifier by a series-resonant passive network that provides both input matching and voltage amplification. The first fully monolithic subthreshold CMOS receiver was also implemented with integrated subthreshold quadrature LO (Local Oscillator) chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage amplification, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling were combined to lower the total power consumption to 2.6 mW. Extremely compact resistive feedback CMOS low noise amplifiers were presented as a cost-effective alternative to narrow band LNAs using high-Q inductors. Techniques to improve linearity and reduce power consumption were presented. The combination of high linearity, low noise figure, high broadband gain, extremely small die area and low power consumption made the proposed LNA architecture a compelling choice for many wireless applications.Ph.D.Committee Chair: Laskar, Joy; Committee Member: Chakraborty, Sudipto; Committee Member: Chang, Jae Joon; Committee Member: Divan, Deepakraj; Committee Member: Kornegay, Kevin; Committee Member: Tentzeris, Emmanoui

    Design of a RF communication receiver front-end for ultra-low power and voltage applications in a FDSOI 28nm technology

    Get PDF
    The advances in the semiconductor and wireless industry have enabled the expansion of new paradigms, which have given rise to concepts like Internet of Things (IoT). Apart from qualities like size, speed or cost, the ever-increasing demand for autonomy focuses all design efforts in the minimization of power consumption. Scaling technologies and the request to reduce power consumption have pushed designers towards lower supply voltages. Despite the fact that technology scalability allows for faster transistors, radio-frequency (RF) integrated circuit (IC) design accuses the reduction of the voltage supply through frequency response degradation, which significantly deteriorates the overall performance. Analog and RF circuits in highend applications require substantial gate voltage overdrive to maintain device speed, which further complicates the design due to the reduction of voltage headroom. As a consequence, the necessity to develop circuit topologies capable to deal with low-power and low-voltage stringent constraints well suited to applications requiring long battery life and low cost emerges. This work aims to implement a low-noise amplifier and mixer stages of a radio-frequency receiver front-end working under an ultra-low power (< 100 ?W) and ultra-low voltage (< 0.8V) scenario while targeting decent overall performance. To cope with the stringent power requirements, 28nm FD-SOI technology will be used to take maximum profit of aggressive forward body bias and enhance transistor performance

    Design of RF Receiver Front end Subsystems with Low Noise Amplifier and Active Mixer for Intelligent Transportation Systems Application

    Get PDF
    This paper presents the design, simulation, and characterization of a novel low-noise amplifier (LNA) and active mixer for intelligent transportation system applications. A low noise amplifier is the key component of RF receiver systems. Design, simulation, and characterization of LNA have been performed to obtain the optimum value of noise figure, gain and reflection coefficient. Proposed LNA achieves measured voltage gains of ~18 dB, reflection coefficients of -20 dB, and noise figures of ~2 dB at 5.9 GHz, respectively. The active mixer is a better choice for a modern receiver system over a passive mixer. Key sight advanced design system in conjunction with the electromagnetic simulation tool, has been to obtain the optimal conversion gain and noise figure of the active mixer. The lower and upper resonant frequencies of mixer have been obtained at 2.45 GHz and 5.25 GHz, respectively. The measured conversion gains at lower and upper frequencies are 12 dB and 10.2 dB, respectively. The measured noise figures at lower and upper frequencies are 5.8 dB and 6.5 dB, respectively. The measured mixer interception point at lower and upper frequencies are 3.9 dBm and 4.2 dBm

    Review Of Mixer And Balun Designs For Uwb Applications

    Get PDF
    This paper presents an important review on mixer and balun designs for several UWB (ultra-wideband) applications that generally operate in frequencies ranging from 3.1 to 10.6 GHz. This paper begins with an introduction of mixer and balun terminologies, followed by discussion and comparison of several types of mixer designs and their performance on conversion gain, noise figure, third-order intercept points input, and port-to-port isolation. Balun plays an important role in RF mixer designs as it converts the single-ended signal coming from LNA into a differential signal that suitable for mixer input terminal. Hence, baluns provide impedance transformation and matching network for structures transition in mixer designs. The previous studies are reviewed and compared in order to gain a better understanding in RF mixers. An alternative design of balun can be suggested to be utilized in mixer designs to produce overall good performance for multi- function operation in UWB applications

    Dual-band FSK receiver and building block design for UWB impulse radio

    Get PDF
    Master'sMASTER OF ENGINEERIN

    Integration of broadband direct-conversion quadrature modulators

    Get PDF
    To increase spectral efficiency, transmitters usually send only one of the information carrying sidebands centered around a single radio-frequency carrier. The close-lying mirror, or image, sideband will be eliminated either by the filtering method or by the phasing method. Since filter Q-values rise in direct relation to the transmitted frequencies, the filtering method is generally not feasible for integrated microwave transmitters. A quadrature modulator realizes the phasing method by combining signals phased at quadrature (i.e. at 90° offsets) to produce a single-sideband (SSB) output. In this way output filtering can be removed or its specifications greatly relieved so as to produce an economical microwave transmitter. The proliferation of integrated circuit (IC) technologies since the 1980s has further boosted the popularity of quadrature modulator as an IC realization makes possible the economical production of two closely matched doubly balanced mixers, which suppress carrier and even-order spurious leakage to circuit output. Another strength of IC is its ability to perform microwave quadrature generation accurately on-chip, and thereby to avoid most of the interconnect parasitics which could ruin high-frequency quadrature signaling. Nevertheless, all quadrature modulator implementations are sensitive to phasing and amplitude errors, which are born as a result of mismatches, from the use of inaccurate differential signaling, and from inadequacies in the phasing circuitry itself. A 2° phase error is easily produced, and it reduces the image-rejection ratio (IRR) to −30 dBc. Therefore, as baseband signals synthesized by digital signal processing (DSP) are sufficiently accurate, this thesis concentrates on analyzing and producing the microwave signal path of a direct-conversion quadrature modulator with special emphasis on broadband, multimode radio-compatible operation. A model of the direct-conversion quadrature modulator operation has been developed, which reveals the effect the circuit non-linearities and mismatch-related offsets have on available performance. Further, theoretical proof is given of the well-known property of improving differential signal balance that cascaded differential pairs exhibit. Among the practical results, a current reuse mixer has been developed, which improves the transmitted signal-to-noise-ratio (SNR) by 3 dB, with a maximum measured dynamic range of +158 dB. The complementary bipolar process was further used to extend the bipolar push-pull stage bandwidth to 9.5 GHz. At the core of this work is the parallel switchable polyphase (PP) filter quadrature generator that was developed, since it makes possible accurate broadband IQ generation without the high loss that usually results from the application of PP filtering. Two IQ modulator prototypes were realized to test simulated and theoretically derived data: the 0.8 ”m SiGe IC achieves an IRR better than −40 dBc over 0.75-3.6 GHz, while the 0.13 ”m digital bulk CMOS IC achieves better than −37 dBc over 0.56-4.76 GHz. For this IRR performance the SiGe prototype boasts the inexpensive solution of integrated baluns, while the CMOS one utilizes a coil-transmission line hybrid transformer at its LO input to drive the switchable PP filters.Taajuuksien kĂ€ytön tehostamiseksi lĂ€hettimet lĂ€hettĂ€vĂ€t yleensĂ€ vain toisen informaatiota sisĂ€ltĂ€vistĂ€ sivukaistoistaan yhdelle radiotaajuuksiselle kantoaallolle keskitettynĂ€. Viereinen peilitaajuus eli sivukaista vaimennetaan joko suodattamalla tai vaiheistamalla signalointia sopivasti. Koska suodattimen hyvyysluvut nousevat suorassa suhteessa kĂ€ytettyyn taajuuteen, ei suodatusmenetelmĂ€ ole yleensĂ€ mahdollinen mikroaaltotaajuusalueen lĂ€hettimissĂ€. Kvadratuurimodulaattori toteuttaa vaiheistusmenetelmĂ€n yhdistĂ€mĂ€llĂ€ 90-asteen vaihesiirroksin vaiheistetut signaalit yksisivukaistaisen lĂ€hetteen tuottamiseksi. NĂ€in voidaan korvata lĂ€hdön suodatus joko kokonaan tai lieventĂ€mĂ€llĂ€ vaadittavia suoritusarvoja, jolloin mikroaaltoalueen lĂ€hetin voidaan tuottaa taloudellisesti. Integroitujen piiriratkaisujen yleistyminen 1980-luvulta lĂ€htien on edesauttanut kvadratuurimodulaattorin suosiota, koska integroidulle piirille voidaan taloudellisesti tuottaa kaksi hyvin ominaisuuksiltaan toisiaan vastaavaa kaksoisbalansoitua sekoitinta, ja nĂ€mĂ€ tunnetusti vaimentavat kantoaaltovuotoa ja parillisia harmoonisia piirin lĂ€hdössĂ€. Toinen integroitujen piirien vahvuus on kyky tarkkaan mikroaaltoalueen kvadratuurisignalointiin samalla piirillĂ€, jolloin vĂ€ltetÀÀn suurin osa kytkentöjen parasiittisista jotka muutoin voisivat tuhota korkeataajuuksisen 90-asteen vaiheistuksen. Kaikki kvadratuurimodulaattorit ovat joka tapauksessa herkkiĂ€ vaiheistus- ja amplitudieroille, joita syntyy komponenttiarvojen satunnaishajonnasta, epĂ€tarkan differentiaalisen signaloinnin kĂ€ytöstĂ€, ja itse vaiheistuspiiristön puutteellisuuksista. Kahden asteen vaihevirhe syntyy helposti, ja tĂ€llöin sivukaistavaimennus heikkenee -30 dBc:n tasolle. TĂ€mĂ€nvuoksi, ja olettaen ettĂ€ digitaalisella signaaliprosessorilla luotu kantataajuuksinen signalointi on riittĂ€vĂ€n tarkkaa, tĂ€mĂ€ vĂ€itöskirja keskittyy kvadratuurimodulaattorin mikroaaltotaajuuksisen signaalipolun analysointiin ja tuottamiseen painottaen erityisesti laajakaistaista, monisovellusradioiden kanssa yhteensopivaa toimivuutta. Kvadratuurimodulaattorin toimintamallia on kehitetty siten, ettĂ€ mallissa huomioidaan epĂ€lineaarisuuksien ja piirielementtien satunnaishajontojen vaikutus saavutettavalle suorituskyvylle. LisĂ€ksi on teoreettisesti todistettu sinĂ€nsĂ€ hyvin tunnettu perĂ€kkĂ€in kytkettyjen vahvistinasteiden differentiaalisen signaloinnin symmetrisyyttĂ€ parantava vaikutus. KĂ€ytĂ€nnön tuloksista voidaan mainita kehitetty virtaakierrĂ€ttĂ€vĂ€ sekoitin, joka parantaa signaali-kohinasuhdetta +3 dB, suurimman mitatun dynaamisen alueen ollessa +158 dB. Samaa komplementaarista bipolaariprosessia kĂ€ytettiin edelleen bipolaarisen vuorovaihe-asteen kaistan levittĂ€misessĂ€ 9.5 GHz:iin. YhtenĂ€ tĂ€mĂ€n työn tĂ€rkeimmistĂ€ tuloksista on kehitetty kytkimin valittavista rinnakkaisista monivaihesuodattimista koostuva kvadratuurigeneraattori, jolla on mahdollista tuottaa laajakaistaista IQ-signalointia ilman suurta hĂ€viötĂ€ joka yleensĂ€ liittyy monivaihesuodattimien kĂ€yttöön. Kaksi IQ-modulaattoriprototyyppiĂ€ toteutettiin simuloitujen ja teoreettisesti mallinnettujen tulosten testaamiseksi: 0.8 ”m SiGe integroitu piiri saavuttaa paremman sivukaistavaimennuksen kuin -40 dBc yli 0.75-3.6 GHz, kun taas 0.13 ”m digitaalipiirien tuottamiseen tarkoitetulla CMOS prosessilla toteutettu integroitu piiri saavuttaa paremman sivukaistavaimennuksen kuin -37 dBc taajuusalueella 0.56-4.76 GHz. NĂ€ihin sivukaistavaimennuksiin SiGe prototyyppi pÀÀsee edullisesti integroiduin symmetrointimuuntajin, kun taas CMOS piirillĂ€ kĂ€ytetÀÀn kela-siirtojohto-tyyppistĂ€ yhdistelmĂ€muuntajaa LO-sisÀÀntulossa josta ajetaan erikseen kytkettĂ€viĂ€ monivaihesuodattimia.reviewe

    Analysis and Design of Wideband Low Noise Amplifier with Digital Control

    Get PDF
    The design issues in designing low noise amplifier (LNA) for Software-Defined-Radio (SDR) are reviewed. An inductor-less wideband low noise amplifier aiming at low frequency band (0.2-2GHz) for Software-Defined-Radio is presented. Shunt-shunt LNA with active feedback is used as the first stage which is carefully optimized for low noise and wide band applications. A digitally controlled second stage is employed to provide an additional 12dB gain control. A novel method is proposed to bypass the first stage without degrading input matching. This LNA is fabricated in a standard 0.18 um CMOS technology. The measurement result shows the proposed LNA has a gain range of 6dB-18dB at high gain mode and -12dB-0dB at low gain mode, as well as a –3dB bandwidth of 2GHz. The noise figure (NF) is 3.5-4.5dB in the high gain setting mode. It consumes 20mW from a 1.8V supply

    Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

    Get PDF
    The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

    Design of Analog-to-Digital Converters with Embedded Mixing for Ultra-Low-Power Radio Receivers

    Get PDF
    In the field of radio receivers, down-conversion methods usually rely on one (or more) explicit mixing stage(s) before the analog-to-digital converter (ADC). These stages not only contribute to the overall power consumption but also have an impact on area and can compromise the receiver’s performance in terms of noise and linearity. On the other hand, most ADCs require some sort of reference signal in order to properly digitize an analog input signal. The implementation of this reference signal usually relies on bandgap circuits and reference buffers to generate a constant, stable, dc signal. Disregarding this conventional approach, the work developed in this thesis aims to explore the viability behind the usage of a variable reference signal. Moreover, it demonstrates that not only can an input signal be properly digitized, but also shifted up and down in frequency, effectively embedding the mixing operation in an ADC. As a result, ADCs in receiver chains can perform double-duty as both a quantizer and a mixing stage. The lesser known charge-sharing (CS) topology, within the successive approximation register (SAR) ADCs, is used for a practical implementation, due to its feature of “pre-charging” the reference signal prior to the conversion. Simulation results from an 8-bit CS-SAR ADC designed in a 0.13 ÎŒm CMOS technology validate the proposed technique
    • 

    corecore