Techniques for low power analog, digital and mixed signal CMOS integrated circuit design

With the continuously expanding of market for portable devices such as wireless communication devices, portable computers, consumer electronics and implantable medical devices, low power is becoming increasingly important in integrated circuits. The low power design can increase operation time and/or utilize a smaller size and lighter-weight battery. In this dissertation, several low power complementary metal-oxide-semiconductor (CMOS) integrated circuit design techniques are investigated. A metal-oxide-semiconductor field effect transistor (MOSFET) can be operated at a lower voltage by forward-biasing the source-substrate junction. This approach has been investigated in detail and used to designing an ultra-low power CMOS operational amplifier for operation at ± 0.4 V. The issue of CMOS latchup and noise has been investigated in detail because of the forward biasing of the substrates of MOSFETs in CMOS. With increasing forward body-bias, the leakage current increases significantly. Dynamic threshold MOSFET (DTMOS) technique is proposed to overcome the drawback which is inherent in a forward-biased MOSFET. By using the DTMOS method with the forward source-body biased MOSFET, two low-power low-voltage CMOS VLSI circuits that of a CMOS analog multiplexer and a Schmitt trigger circuits are designed. In this dissertation, an adaptive body-bias technique is proposed. Adaptive body-bias voltage is generated for several operational frequencies. Another issue, which the chip design community is facing, is the development of portable, cost effective and low power supply voltage. This dissertation proposes a new cost-effective DC/DC converter design in standard 1.5 um n-well CMOS, which adopts a delay-line controller for voltage regulation

Design of a low-voltage CMOS RF receiver for energy harvesting sensor node

In this thesis a CMOS low-power and low-voltage RF receiver front-end is presented. The main objective is to design this RF receiver so that it can be powered by a piezoelectric energy harvesting power source, included in a Wireless Sensor Node application. For this type of applications the major requirements are: the low-power and low-voltage operation, the reduced area and cost and the simplicity of the architecture. The system key blocks are the LNA and the mixer, which are studied and optimized with greater detail, achieving a good linearity, a wideband operation and a reduced introduction of noise. A wideband balun LNA with noise and distortion cancelling is designed to work at a 0.6 V supply voltage, in conjunction with a double-balanced passive mixer and subsequent TIA block. The passive mixer operates in current mode, allowing a minimal introduction of voltage noise and a good linearity. The receiver analog front-end has a total voltage conversion gain of 31.5 dB, a 0.1 - 4.3 GHz bandwidth, an IIP3 value of -1.35 dBm, and a noise figure lower than 9 dB. The total power consumption is 1.9 mW and the die area is 305x134.5 m2, using a standard 130 nm CMOS technology

Utilizing Unconventional CMOS Techniques for Low Voltage Low Power Analog Circuits Design for Biomedical Applications

Tato disertační práce se zabývá navržením nízkonapěťových, nízkopříkonových analogových obvodů, které používají nekonvenční techniky CMOS. Lékařská zařízení na bateriové napájení, jako systémy pro dlouhodobý fyziologický monitoring, přenosné systémy, implantovatelné systémy a systémy vhodné na nošení, musí být male a lehké. Kromě toho je nutné, aby byly tyto systémy vybaveny baterií s dlouhou životností. Z tohoto důvodu převládají v biomedicínských aplikacích tohoto typu nízkopříkonové integrované obvody. Nekonvenční techniky jako např. využití transistorů s řízeným substrátem (Bulk-Driven “BD”), s plovoucím hradlem (Floating-Gate “FG”), s kvazi plovoucím hradlem (Quasi-Floating-Gate “QFG”), s řízeným substrátem s plovoucím hradlem (Bulk-Driven Floating-Gate “BD-FG”) a s řízeným substrátem s kvazi plovoucím hradlem (Bulk-Driven Quasi-Floating-Gate “BD-QFG”), se v nedávné době ukázaly jako efektivní prostředek ke zjednodušení obvodového zapojení a ke snížení velikosti napájecího napětí směrem k prahovému napětí u tranzistorů MOS (MOST). V práci jsou podrobně představeny nejdůležitější charakteristiky nekonvenčních technik CMOS. Tyto techniky byly použity pro vytvoření nízko napěťových a nízko výkonových CMOS struktur u některých aktivních prvků, např. Operational Transconductance Amplifier (OTA) založené na BD, FG, QFG, a BD-QFG techniky; Tunable Transconductor založený na BD MOST; Current Conveyor Transconductance Amplifier (CCTA) založený na BD-QFG MOST; Z Copy-Current Controlled-Current Differencing Buffered Amplifier (ZC-CC-CDBA) založený na BD MOST; Winner Take All (WTA) and Loser Take All (LTA) založený na BD MOST; Fully Balanced Four-Terminal Floating Nullor (FBFTFN) založený na BD-QFG technice. Za účelem ověření funkčnosti výše zmíněných struktur, byly tyto struktury použity v několika aplikacích. Výkon navržených aktivních prvků a příkladech aplikací je ověřován prostřednictvím simulačních programů PSpice či Cadence za použití technologie 0.18 m CMOS.This doctoral thesis deals with designing ultra-low-voltage (LV) low-power (LP) analog circuits utilizing the unconventional CMOS techniques. Battery powered medical devices such as; long term physiological monitoring, portable, implantable, and wearable systems need to be small and lightweight. Besides, long life battery is essential need for these devices. Thus, low-power integrated circuits are always paramount in such biomedical applications. Recently, unconventional CMOS techniques i.e. Bulk-Driven (BD), Floating-Gate (FG), Quasi-Floating-Gate (QFG), Bulk-Driven Floating-Gate (BD-FG) and Bulk-Driven Quasi-Floating-Gate (BD-QFG) MOS transistors (MOSTs) have revealed as effective devices to reduce the circuit complexity and push the voltage supply of the circuit towards threshold voltage of the MOST. In this work, the most important features of the unconventional CMOS techniques are discussed in details. These techniques have been utilized to perform ultra-LV LP CMOS structures of several active elements i.e. Operational Transconductance Amplifier (OTA) based on BD, FG, QFG, and BD-QFG techniques; Tunable Transconductor based on BD MOST; Current Conveyor Transconductance Amplifier (CCTA) based on BD-QFG MOST; Z Copy-Current Controlled-Current Differencing Buffered Amplifier (ZC-CC-CDBA) based on BD MOST; Winner Take All (WTA) and Loser Take All (LTA) based on BD MOST; Fully Balanced Four-Terminal Floating Nullor (FBFTFN) based on BD-QFG technique. Moreover, to verify the workability of the proposed structures, they were employed in several applications. The performance of the proposed active elements and their applications were investigated through PSpice or Cadence simulation program using 0.18 m CMOS technology.

New Possibilities In Low-voltage Analog Circuit Design Using Dtmos Transistors

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2013(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2013Bu çalışmada DTMOS yaklaşımı çok düşük besleme gerilimlerinde çalışan çok düşük güç tüketimli devrelere başarıyla uygulanmıştır. Tasarlanan devreler arasında OTA, OP-AMP, CCII gibi analog aktif yapı blokları, çarpma devresi, sadece-MOS yapılar gibi devreler bulunmaktadır. Tasarlanan devreler SPICE benzetimleri ile doğrulanmıştır. İleri yönde gövde kutuplamaya bağlı olarak DTMOS transistorun yapısından kaynaklanan, efektif olarak düşük eşik gerilimli çalışma özelliği nedeniyle, çok düşük güç tüketimli ve çok düşük gerilimli devrelerde DTMOS yaklaşımının geçerli bir alternatif olduğu bu çalışmayla gösterilmiştir. DTMOS yaklaşımının geniş bir alanda çeşitlilik gösteren analog devre yapılarında çok düşük besleme gerilimlerinde bile kabul edilebilir bir performansla kullanılabileceği bulunmuştur.In this study, DTMOS approach to the design of ultra low-voltage and ultra low-power analog circuits, has been successfully applied to the circuits ranging from EEG filtering circuits, speech processing filters in hearing aids, multipliers, analog active building blocks: OTA, OP-AMP, CCII to MOS-only circuits. The proposed circuits are verified with SPICE simulations. It is found that in designing ultra low-voltage, ultra low-power analog circuits, DTMOS approach is a viable alternative due to its inherent characteristic of effective low threshold voltage behaviour under forward body bias. This approach can be applied to several analog application subjects with acceptable performance under even ultra low supply voltages.DoktoraPh

A sub 1V bandgap reference circuit

This thesis proposes a novel technique for a low supply voltage temperature-independent reference voltage. With the scaling of supply voltages, the threshold voltages don’t scale proportionally and thus low supply reference circuits have replaced the conventional bandgap reference circuit. The first chapter of this work discusses the conventional bandgap references (The Widlar and Brokaw references). The terminology used in the bandgap world is introduced here. The second chapter investigates the existing low supply voltage reference circuits with their advantages and the limitations. A table discussing all the investigated circuits is provided towards the end of the chapter as a summary. Chapter Three proposes a novel technique to generate a temperature-independent voltage which does not use an operational amplifier. This chapter also provides a mathematical understanding for behavior of the circuit. Chapter Four talks about two variations of the proposed architecture. These variations are designed in order to improve the performance of the proposed circuit against power supply variations. Each one of them has its own merits and drawbacks. Finally Chapter Five discusses the effects of process variations and transient response of the proposed circuit. A digital trimming scheme using an EE-PROM is proposed to manage almost all of the process variation effects on the circuit

Rectification, amplification and switching capabilities for energy harvesting systems: power management circuit for piezoelectric energy harvester

Dissertação de mestrado em Biomedical EngineeringA new energy mechanism needs to be addressed to overcome the battery dependency, and consequently extend Wireless Sensor Nodes (WSN) lifetime effectively. Energy Harvesting is a promising technology that can fulfill that premise. This work consists of the realization of circuit components employable in a management system for a piezoelectric-based energy harvester, with low power consumption and high efficiency. The implementation of energy harvesting systems is necessary to power-up front-end applications without any battery. The input power and voltage levels generated by the piezoelectric transducer are relatively low, especially in small-scale systems, as such extra care has to be taken in power consumption and efficiency of the circuits. The main contribution of this work is a system capable of amplifying, rectifying and switching the unstable signal from an energy harvester source. The circuit components are designed based on 0.13 Complementary Metal-Oxide-Semiconductor (CMOS) technology. An analog switch, capable of driving the harvesting circuit at a frequency between 1 and 1 , with proper temperature behaviour, is designed and verified. An OFF resistance of 520.6 Ω and isolation of −111.24 , grant excellent isolation to the circuit. The designed voltage amplifier is capable of amplifying a minor signal with a gain of 42.56 , while requiring low power consumption. The output signal is satisfactorily amplified with a reduced offset voltage of 8 . A new architecture of a two-stage active rectifier is proposed. The power conversion efficiency is 40.4%, with a voltage efficiency of up to 90%. Low power consumption of 17.7 is achieved by the rectifier, with the embedded comparator consuming 113.9 . The outcomes validate the circuit’s power demands, which can be used for other similar applications in biomedical, industrial, and commercial fields.Para combater a dependência dos dispositivos eletrónicos relativamente ás baterias é necessário um novo sistema energético, que permita prolongar o tempo de vida útil dos mesmos. Energy Harvesting é uma tecnologia promissora utilizada para alimentar dispositivos sem bateria. Este trabalho consiste na realização de componentes empregáveis num circuito global para extrair energia a partir ds vibrações de um piezoelétricos com baixo consumo de energia e alta eficiência. Os níveis de potência e voltagem gerados pelo transdutor piezoelétrico são relativamente baixos, especialmente em sistemas de pequena escala, por isso requerem cuidado extra relativamente ao consumo de energia e eficiência dos circuitos. A principal contribuição deste trabalho é um sistema apropriado para amplificar, retificar e alternar o sinal instável proveniente de uma fonte de energy harvesting. Os componentes do sistema são implementados com base na tecnologia CMOS com 0.13 . Um interruptor analógico capaz de modelar a frequência do sinal entre 1 e 1 e estável perante variações de temperatura, é implementado. O circuito tem um excelente isolamento de −111.24 , devido a uma resistência OFF de 520.6 Ω. O amplificador implementado é apto a amplificar um pequeno sinal com um ganho de 42.56 e baixo consumo. O sinal de saída é satisfatoriamente amplificado com uma voltagem de offset de 8 . Um retificador ativo de dois estágios com uma nova arquitetura é proposto. A eficiência de conversão de energia atinge os 40.4%, com uma eficiência de voltagem até 90%. O retificador consome pouca energia, apenas 17.7 , incorporando um comparador de 113.9 . Os resultados validam as exigências energéticas do circuito, que pode ser usado para outras aplicações similares no campo biomédico, industrial e comercial

A wideband linear tunable CDTA and its application in field programmable analogue array

This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio

A Two Channel Analog Front end Design AFE Design with Continuous Time Σ-Δ Modulator for ECG Signal

In this context, the AFE with 2-channels is described, which has high impedance for low power application of bio-medical electrical activity. The challenge in obtaining accurate recordings of biomedical signals such as EEG/ECG to study the human body in research work. This paper is to propose Multi-Vt in AFE circuit design cascaded with CT modulator. The new architecture is anticipated with two dissimilar input signals filtered from 2-channel to one modulator. In this methodology, the amplifier is low powered multi-VT Analog Front-End which consumes less power by applying dual threshold voltage. Type -I category 2 channel signals of the first mode: 50 and 150 Hz amplified from AFE are given to 2nd CT sigma-delta ADC. Depict the SNR and SNDR as 63dB and 60dB respectively, consuming the power of 11mW. The design was simulated in a 0.18 um standard UMC CMOS process at 1.8V supply. The AFE measured frequency response from 50 Hz to 360 Hz, depict the SNR and SNDR as 63dB and 60dB respectively, consuming the power of 11mW. The design was simulated in 0.18 m standard UMC CMOS process at 1.8V supply. The AFE measured frequency response from 50 Hz to 360 Hz, programmable gains from 52.6 dB to 72 dB, input referred noise of 3.5 μV in the amplifier bandwidth, NEF of 3

A 0.3 V rail-to-rail ultra-low-power OTA with improved bandwidth and slew rate

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier