Recent Advances in Ambipolar Transistors for Functional Applications

Ambipolar transistors represent a class of transistors where positive (holes) and negative (electrons) charge carriers both can transport concurrently within the semiconducting channel. The basic switching states of ambipolar transistors are comprised of common offâ state and separated onâ state mainly impelled by holes or electrons. During the past years, diverse materials are synthesized and utilized for implementing ambipolar charge transport and their further emerging applications comprising ambipolar memory, synaptic, logic, and lightâ emitting transistors on account of their special bidirectional carrierâ transporting characteristic. Within this review, recent developments of ambipolar transistor field involving fundamental principles, interface modifications, selected semiconducting material systems, device structures, ambipolar characteristics, and promising applications are highlighted. The existed challenges and prospective for researching ambipolar transistors in electronics and optoelectronics are also discussed. It is expected that the review and outlook are well timed and instrumental for the rapid progress of academic sector of ambipolar transistors in lighting, display, memory, as well as neuromorphic computing for artificial intelligence.Ambipolar transistors represent transistors that allow synchronous transport of electrons and holes and their accumulation within semiconductors. This review provides a comprehensive summary of recent advances in various semiconducting materials realized in ambipolar transistors and their functional memory, synapse, logic, as well as lightâ emitting applications.Peer Reviewedhttps://deepblue.lib.umich.edu/bitstream/2027.42/151885/1/adfm201902105_am.pdfhttps://deepblue.lib.umich.edu/bitstream/2027.42/151885/2/adfm201902105.pd

ENHANCEMENT OF MARKOV RANDOM FIELD MECHANISM TO ACHIEVE FAULT-TOLERANCE IN NANOSCALE CIRCUIT DESIGN

As the MOSFET dimensions scale down towards nanoscale level, the reliability of circuits based on these devices decreases. Hence, designing reliable systems using these nano-devices is becoming challenging. Therefore, a mechanism has to be devised that can make the nanoscale systems perform reliably using unreliable circuit components. The solution is fault-tolerant circuit design. Markov Random Field (MRF) is an effective approach that achieves fault-tolerance in integrated circuit design. The previous research on this technique suffers from limitations at the design, simulation and implementation levels. As improvements, the MRF fault-tolerance rules have been validated for a practical circuit example. The simulation framework is extended from thermal to a combination of thermal and random telegraph signal (RTS) noise sources to provide a more rigorous noise environment for the simulation of circuits build on nanoscale technologies. Moreover, an architecture-level improvement has been proposed in the design of previous MRF gates. The redesigned MRF is termed as Improved-MRF. The CMOS, MRF and Improved-MRF designs were simulated under application of highly noisy inputs. On the basis of simulations conducted for several test circuits, it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10 times more noise-tolerant than the CMOS alternatives. The number of transistors, on the other hand increased from a factor of 9 to 15 from MRF to Improved-MRF respectively (as compared to the CMOS). Therefore, in order to provide a trade-off between reliability and the area overhead required for obtaining a fault-tolerant circuit, a novel parameter called as ‘Reliable Area Index’ (RAI) is introduced in this research work. The value of RAI exceeds around 1.3 and 40 times for MRF and Improved-MRF respectively as compared to CMOS design which makes Improved- MRF to be still 30 times more efficient circuit design than MRF in terms of maintaining a suitable trade-off between reliability and area-consumption of the circuit

Crosstalk computing: circuit techniques, implementation and potential applications

Title from PDF of title [age viewed January 32, 2022Dissertation advisor: Mostafizur RahmanVitaIncludes bibliographical references (page 117-136)Thesis (Ph.D.)--School of Computing and Engineering. University of Missouri--Kansas City, 2020This work presents a radically new computing concept for digital Integrated Circuits (ICs), called Crosstalk Computing. The conventional CMOS scaling trend is facing device scaling limitations and interconnect bottleneck. The other primary concern of miniaturization of ICs is the signal-integrity issue due to Crosstalk, which is the unwanted interference of signals between neighboring metal lines. The Crosstalk is becoming inexorable with advancing technology nodes. Traditional computing circuits always tries to reduce this Crosstalk by applying various circuit and layout techniques. In contrast, this research develops novel circuit techniques that can leverage this detrimental effect and convert it astutely to a useful feature. The Crosstalk is engineered into a logic computation principle by leveraging deterministic signal interference for innovative circuit implementation. This research work presents a comprehensive circuit framework for Crosstalk Computing and derives all the key circuit elements that can enable this computing model. Along with regular digital logic circuits, it also presents a novel Polymorphic circuit approach unique to Crosstalk Computing. In Polymorphic circuits, the functionality of a circuit can be altered using a control variable. Owing to the multi-functional embodiment in polymorphic-circuits, they find many useful applications such as reconfigurable system design, resource sharing, hardware security, and fault-tolerant circuit design, etc. This dissertation shows a comprehensive list of polymorphic logic gate implementations, which were not reported previously in any other work. It also performs a comparison study between Crosstalk polymorphic circuits and existing polymorphic approaches, which are either inefficient due to custom non-linear circuit styles or propose exotic devices. The ability to design a wide range of polymorphic logic circuits (basic and complex logics) compact in design and minimal in transistor count is unique to Crosstalk Computing, which leads to benefits in the circuit density, power, and performance. The circuit simulation and characterization results show a 6x improvement in transistor count, 2x improvement in switching energy, and 1.5x improvement in performance compared to counterpart implementation in CMOS circuit style. Nevertheless, the Crosstalk circuits also face issues while cascading the circuits; this research analyzes all the problems and develops auxiliary circuit techniques to fix the problems. Moreover, it shows a module-level cascaded polymorphic circuit example, which also employs the auxiliary circuit techniques developed. For the very first time, it implements a proof-of-concept prototype Chip for Crosstalk Computing at TSMC 65nm technology and demonstrates experimental evidence for runtime reconfiguration of the polymorphic circuit. The dissertation also explores the application potentials for Crosstalk Computing circuits. Finally, the future work section discusses the Electronic Design Automation (EDA) challenges and proposes an appropriate design flow; besides, it also discusses ideas for the efficient implementation of Crosstalk Computing structures. Thus, further research and development to realize efficient Crosstalk Computing structures can leverage the comprehensive circuit framework developed in this research and offer transformative benefits for the semiconductor industry.Introduction and Motivation -- More Moore and Relevant Beyond CMOS Research Directions -- Crosstalk Computing -- Crosstalk Circuits Based on Perception Model -- Crosstalk Circuit Types -- Cascading Circuit Issues and Sollutions -- Existing Polymorphic Circuit Approaches -- Crosstalk Polymorphic Circuits -- Comparison and Benchmarking of Crosstalk Gates -- Practical Realization of Crosstalk Gates -- Poential Applications -- Conclusion and Future Wor

Adaptive extreme edge computing for wearable devices

Wearable devices are a fast-growing technology with impact on personal healthcare for both society and economy. Due to the widespread of sensors in pervasive and distributed networks, power consumption, processing speed, and system adaptation are vital in future smart wearable devices. The visioning and forecasting of how to bring computation to the edge in smart sensors have already begun, with an aspiration to provide adaptive extreme edge computing. Here, we provide a holistic view of hardware and theoretical solutions towards smart wearable devices that can provide guidance to research in this pervasive computing era. We propose various solutions for biologically plausible models for continual learning in neuromorphic computing technologies for wearable sensors. To envision this concept, we provide a systematic outline in which prospective low power and low latency scenarios of wearable sensors in neuromorphic platforms are expected. We successively describe vital potential landscapes of neuromorphic processors exploiting complementary metal-oxide semiconductors (CMOS) and emerging memory technologies (e.g. memristive devices). Furthermore, we evaluate the requirements for edge computing within wearable devices in terms of footprint, power consumption, latency, and data size. We additionally investigate the challenges beyond neuromorphic computing hardware, algorithms and devices that could impede enhancement of adaptive edge computing in smart wearable devices

ENHANCEMENT OF MARKOV RANDOM FIELD MECHANISM TO ACHIEVE FAULT-TOLERANCE IN NANOSCALE CIRCUIT DESIGN

As the MOSFET dimensions scale down towards nanoscale level, the reliability of circuits based on these devices decreases. Hence, designing reliable systems using these nano-devices is becoming challenging. Therefore, a mechanism has to be devised that can make the nanoscale systems perform reliably using unreliable circuit components. The solution is fault-tolerant circuit design. Markov Random Field (MRF) is an effective approach that achieves fault-tolerance in integrated circuit design. The previous research on this technique suffers from limitations at the design, simulation and implementation levels. As improvements, the MRF fault-tolerance rules have been validated for a practical circuit example. The simulation framework is extended from thermal to a combination of thermal and random telegraph signal (RTS) noise sources to provide a more rigorous noise environment for the simulation of circuits build on nanoscale technologies. Moreover, an architecture-level improvement has been proposed in the design of previous MRF gates. The redesigned MRF is termed as Improved-MRF. The CMOS, MRF and Improved-MRF designs were simulated under application of highly noisy inputs. On the basis of simulations conducted for several test circuits, it is found that Improved-MRF circuits are 400 whereas MRF circuits are only 10 times more noise-tolerant than the CMOS alternatives. The number of transistors, on the other hand increased from a factor of 9 to 15 from MRF to Improved-MRF respectively (as compared to the CMOS). Therefore, in order to provide a trade-off between reliability and the area overhead required for obtaining a fault-tolerant circuit, a novel parameter called as ‘Reliable Area Index’ (RAI) is introduced in this research work. The value of RAI exceeds around 1.3 and 40 times for MRF and Improved-MRF respectively as compared to CMOS design which makes Improved- MRF to be still 30 times more efficient circuit design than MRF in terms of maintaining a suitable trade-off between reliability and area-consumption of the circuit

AI/ML Algorithms and Applications in VLSI Design and Technology

An evident challenge ahead for the integrated circuit (IC) industry in the nanometer regime is the investigation and development of methods that can reduce the design complexity ensuing from growing process variations and curtail the turnaround time of chip manufacturing. Conventional methodologies employed for such tasks are largely manual; thus, time-consuming and resource-intensive. In contrast, the unique learning strategies of artificial intelligence (AI) provide numerous exciting automated approaches for handling complex and data-intensive tasks in very-large-scale integration (VLSI) design and testing. Employing AI and machine learning (ML) algorithms in VLSI design and manufacturing reduces the time and effort for understanding and processing the data within and across different abstraction levels via automated learning algorithms. It, in turn, improves the IC yield and reduces the manufacturing turnaround time. This paper thoroughly reviews the AI/ML automated approaches introduced in the past towards VLSI design and manufacturing. Moreover, we discuss the scope of AI/ML applications in the future at various abstraction levels to revolutionize the field of VLSI design, aiming for high-speed, highly intelligent, and efficient implementations

Craniomaxillofacial bone tissue engineering : a translational approach

Bone tissue engineering (BTE) has shown a great promise in providing the next generation medical bioimplants for treating bone defects. However, BTE faces many obstacles which need to be addressed for promoting translatability. The objective of this thesis work was to explore clinically translatable tissue engineering approaches for the management of craniomaxillofacial bone defects. The role of the employed cells has witnessed a critical turning point towards an increased appreciation of the cellular paracrine effects. This paracrine effect is mediated via secreted proteins and released membrane-bound vesicles called extracellular vesicles (EVs). For advancing our knowledge about the biological roles of EVs, we employed RNA sequencing to provide a comprehensive overview of the expression profiles of small non-coding transcripts carried by the EVs derived from human adipose tissue stromal/stem cells (AT-MSCs) and human pluripotent stem cells (hPSCs). Our findings revealed distinctive small non-coding RNA profiles from hPSCs and AT-MSCs EVs. The regulatory miRNAs of stem cells at cellular level are also present in their EVs, indicating an important regulatory role which is mediated via EVs. Vascularization is the key challenge for BTE applications in large bone defects. The local delivery of growth factors leads to short lived effects. Small molecule chemicals feature alternative cost-effective bioactive agents with better stability. We assessed the ability of two small molecules; DMOG and baicalein, in triggering the proangiogenic secretome of AT-MSCs in vitro. Additionally, other effects, such as proliferation and osteogenic differentiation of AT-MSCs were assessed. DMOG and baicalein efficiently stabilized the hypoxia-inducible factor (HIF-1α) and upregulated proangiogenic cytokines, e.g., vascular endothelial growth factor (VEGF) and platelet derived growth factor-BB (PDGF-BB) of AT-MSCs in normoxic conditions. These effects were further associated with upregulated stemness-related gene expression, slowed proliferation, and reduced osteogenic potential. Chemically-induced hypoxia maintained the stemness and self-renewal properties of AT-MSCs, while enhancing their proangiogenic potential. The in vivo bioreactor (IVB) concept combines the potential of BTE and reconstructive surgery by employing the patient body for prefabricating new prevascularized tissues. Ideally, IVB should minimize the need for exogenous growth factors or cells and harness the native regenerative potential of employed tissues. Using acellular alloplastic bone blocks, we compared muscle-IVB with and without periosteal/pericranial grafts and flaps for prefabricating tissue engineered bone (TEB) flaps. We also assessed their functional outcomes in reconstructing a mandibular defect in an ovine model. The employment of vascularized periosteal flaps did result in more robust vascularization as compared to other IVB techniques. Both the periosteal grafts and periosteal flaps enhanced the performance of the prefabricated TEB flaps after transplantation into a mechanically stimulated bony microenvironment. However, more new bone formation and biomaterial remodeling was associated with the vascularized periosteal flaps.Luukudosteknologiasta (BTE) odotetaan uuden sukupolven kudossiirteitä luukudosvaurioiden hoitoon. Tämän väitöskirjan tavoitteena oli tutkia kliinisesti sovellettavia kudosteknologisia lähestymistapoja kallon ja kasvojen luuvaurioiden korjaamiseksi. Solujen rooli kudosteknologiassa on muuttunut merkittävästi viime vuosikymmenellä kohdistaen tutkimuksen yhä enemmän solujen parakriinivaikutukseen, joka välittyy erittyvien proteiinien ja ekstrasellulaarivesikkelien (EV) kautta. Ymmärtääksemme ihmisen kantasoluista peräisin olevien EV:en roolin kudosteknologiassa, sekvensoimme näiden sisältämien pienten ei-koodaavien RNA-molekyylien ilmentymisprofiilit rasvakudoksen strooma/kantasoluista (AT-MSC) ja pluripotenteista kantasoluista (hPSC). Totesimme selvät eroavaisuudet näiden välillä, osoittaen solukommunikaation etenevän myös EVvälitteisesti. Vaskularisaatio on keskeinen haaste BTE-sovelluksissa suurissa luukudosvaurioissa ja on todettu, että paikallinen kasvutekijöiden annostelu vaikuttaa vain lyhytaikaisesti. Pienimolekyylisissä yhdisteissä on tarjolla vaihtoehtoisia kustannustehokkaita bioaktiivisia aineita, joista tutkimme kahden, dimetyylioksalyyliglysiinin (DMOG) ja baikaleiinin, vaikutusta AT-MSC:n proangiogeenisen sekretomiin. DMOG ja baikaleiini stabiloivat tehokkaasti hypoksiaa indusoivaa tekijää (HIF-1a) ja säätelivät proangiogeenisia sytokiineja, kuten verisuonen endoteelikasvutekijää (VEGF) ja verihiutalekasvutekijää (PDGF-BB), mikä osoitti kemiallisesti indusoidun hypoksian edistävän AT-MSC:n proangiogeenista potentiaalia. In vivo bioreaktorikonseptin (IVB) tarkoituksena on hyödyntää potilaan omaa kehoa uudiskudosten verisuonittumisessa, poistaen paikallisesti annettujen kasvutekijöiden tai -solujen tarpeen hyödyntämällä kudosten luontaista uusiutumiskykyä. Tutkimuksessa testattiin lammasmallissa tehostetun luutumisen ja verisuonittumisen aikaansaamiseksi lihas- ja luukalvosiirteitä sekä -kielekkeitä alloplastisilla luusiirteillä. IVB-rakenteiden toiminnallisuus arvioitiin rekonstruoimalla näiden avulla leukakulman luuvaurioita. Verisuonittunut luukalvokieleke-IVB johti voimakkaimpaan verisuonittumiseen ja tehostettuun luuvaurion korjaantumiseen leukakulmassa verrattuna muihin IVB-tekniikoihin

Miniaturized Transistors, Volume II

In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before