FPGA-based implementation of electronic abacus using Altera DE2 board

The development of electronic abacus is to integrate the use of abacus along with electronic devices which offers better visualisation of the abacus operations. The main focus of this application is to assist the primary school students‟ in validating a fundamental arithmetic operation by using an abacus. The electronic abacus is developed by integrating an abacus, abacus decoder module and FPGA-based processor. DE2 115 is chosen as the development module and VHDL as main programming language. The arithmetic algorithm developed for the electronic abacus is limited to the computational of whole numbers only. The electronic abacus is operational in two modes, display mode and arithmetic mode. In the display mode, the abacus beads position at column 1 until column 7is displayed as numerical representation on the LCD screen. A computation of arithmetic operations with less than three operatorsare available in the arithmetic modewith the capability ofdisplaying the negative numerical and infinite value. The implementation of integrating an abacus with electronic devices will hopefullycontribute in the development of more lively and interesting teaching approach by using this ancient apparatus

Enhancement of Exon Regions Recognition in Gene Sequences Using a Radix -4 Multi-valued Logic with DSP Approach

Numerous levels of concepts perform logical designand logical representations in an efficient manner. In typical and quantum theories of computation, Binary logic and Boolean algebra occupies an imperative place. But they havethe limitation of representing signals or sequences by using either binary ‘1’ or ‘0’. This has major drawbacks that the neutralities or any intermediate values are ignored which are essential in most of the applications. Because of the occurrence of such situations it is the need of the hour to look into other alternative logics in order to fulfill the necessities of the user in their respective applications. The binary logic can be replaced by Multi-Valued Logic (MVL), which grabs the positions of the major applications because of the ability to provide representation by using more than two values.As most of the significant applications are based on the logical sequences, the multi-valued logic shines because of its thriving feature. Genomic signal processing, a novel research area in bioinformatics,is one of the foremost applications which involve the operations of logical sequences. It is concerned with the digital signal representations and analysis of genomic data.Determination of the coding region in DNA sequence is one of the genomic operations.This leads to the identification of the characteristics of the gene which in turn finds out an individual’s behavior. In order to extract the coding regions on the basis of logical sequences a number of techniques have been proposed by researchers. But most of the works utilized binary logic, which lead to the problem of losing some of the coding regions and incorrectly recognizing non-coding regions as the coding regions. Hereby,we are proposing an approach for recognizing the exon regions from a gene sequence based on the multi-valued logic. In this approach, we have utilized fourlevel logical system, termed as quaternary logic for the representation of gene sequences and so that we recognize theexon regions from the DNA sequence

Mental Arithmetic across Three Language Groups

Mental arithmetic performance was investigated among three language groups (English monolinguals, Chinese-English bilinguals, and Spanish-English bilinguals). Participants solved both small and large numerosity arithmetic problems in addition and multiplication and reported their solution strategies. All groups performed better in small problems than in large ones and better in addition than in multiplication, especially for a large size set. The results revealed all three groups performed equally well in solving problems correctly. Spanish-English bilinguals were equivalent to their English monolingual peers. However, Chinese-English bilinguals outperformed the other two groups in solution speed, especially when problems consisted of large numbers. No group differences were found in the frequency of using retrieval strategies to solve problems. Linguistic influence and other possible factors were discussed to explain the mental arithmetic advantage for Chinese-English bilinguals relative to other groups

Designing Approximate Computing Circuits with Scalable and Systematic Data-Driven Techniques

Semiconductor feature size has been shrinking significantly in the past decades. This decreasing trend of feature size leads to faster processing speed as well as lower area and power consumption. Among these attributes, power consumption has emerged as the primary concern in the design of integrated circuits in recent years due to the rapid increasing demand of energy efficient Internet of Things (IoT) devices. As a result, low power design approaches for digital circuits have become of great attractive in the past few years. To this end, approximate computing in hardware design has emerged as a promising design technique. It provides design opportunities to improve timing and energy efficiency by relaxing computing quality. This technique is feasible because of the error-resiliency of many emerging resource-hungry computational applications such as multimedia processing and machine learning. Thus, it is reasonable to utilize this characteristic to trade an acceptable amount of computing quality for energy saving. In the literature, most prior works on approximate circuit design focus on using manual design strategies to redesign fundamental computational blocks such as adders and multipliers. However, the manual design techniques are not suitable for system level hardware due to much higher design complexity. In order to tackle this challenge, we focus on designing scalable, systematic and general design methodologies that are applicable on any circuits. In this paper, we present two novel approximate circuit design methods based on machine learning techniques. Both methods skip the complicated manual analysis steps and primarily look at the given input-error pattern to generate approximate circuits. Our first work presents a framework for designing compensation block, an essential component in many approximate circuits, based on feature selection. Our second work further extends and optimizes this framework and integrates data-driven consideration into the design. Several case studies on fixed-width multipliers and other approximate circuits are presented to demonstrate the effectiveness of the proposed design methods. The experimental results show that both of the proposed methods are able to automatically and efficiently design low-error approximate circuits

The art and architecture of mathematics education: a study in metaphors

This chapter presents the summary of a talk given at the Eighth European Summer University, held in Oslo in 2018. It attempts to show how art, literature, and history, can paint images of mathematics that are not only useful but relevant to learners as they can support their personal development as well as their appreciation of mathematics as a discipline. To achieve this goal, several metaphors about and of mathematics are explored

Attuning to the mathematics of difference: Haptic constructions of number.

CAPTeaM develops and trials activities that Challenge Ableist Perspectives on the Teaching of Mathematics. The project involves teachers and researchers from the UK and Brazil in reflecting upon the practices that enable or disable the participation of disabled learners in mathematics. In this paper, we focus on two themes that emerged from data analyses generated in the first phase of the study: deconstructing the notion of the normal mathematics student/classroom and attuning mathematics teaching strategies to student diversity. Here, we address these themes through exemplifying participants’ haptic constructions of number in the context of a multiplication task in terms of four strategies they devise: “counting fingers”; “tracing the sum”; “negotiating signs to indicate place value”; “decomposing”

Teachers' use of resources for mathematics teaching: The case of teaching trigonometry.

This paper draws on the documentational approach and knowledge quartet to analyse a trigonometry Year 13 lesson of a secondary mathematics teacher who uses a range of paper based and electronic resources. Data were collected during one lesson observation and a follow-up interview with the teacher. Analysis identifies the resources and schemes of use of these resources: aims of the teaching activity, rules of actions, operational invariants and inferences in relation to the trigonometry lesson but also in relation to Year 13 teaching, especially towards student preparation for the exams. It also explores this teacher’s work in the class by using the different dimensions of the knowledge quartet: foundation, transformation, connection and contingency. The findings explore teacher’s use of resources and the potencies of using the knowledge quartet in tandem with the documentational approach

2.5D Chiplet Architecture for Embedded Processing of High Velocity Streaming Data

This dissertation presents an energy efficient 2.5D chiplet-based architecture for real-time probabilistic processing of high-velocity sensor data, from an autonomous real-time ubiquitous surveillance imaging system. This work addresses problems at all levels of description. At the lowest physical level, new standard cell libraries have been developed for ultra-low voltage CMOS synthesis, as well as custom SRAM memory blocks, and mixed-signal physical true random number generators based on the perturbation of Sigma-Delta structures using random telegraph noise (RTN) in single transistor devices. At the chip level architecture, an innovative compact buffer-less switched circuit mesh network on chip (NoC) capable of reaching very high throughput (1.6Tbps), finite packet delay delivery, free from packet dropping, and free from dead-locks and live-locks, was designed for this chiplet-based solution. Additionally, a second NoC connecting processors in the network, was implemented based on token-rings, allowing access to external DDR memory. Furthermore, a new clock tree distribution network, and a wide bandwidth DRAM physical interface have been designed to address the data flow requirements within and across chiplets. At the algorithm and representation levels, the Online Change Point Detection (CPD) algorithm has been implemented for on-line learning of background-foreground segmentation. Instead of using traditional binary representation of numbers, this architecture relies on unconventional processing of signals using a bio-inspired (spike-based) unary representation of numbers, where these numbers are represented in a stochastic stream of Bernoulli random variables. By using this representation, probabilistic algorithms can be executed in a native architecture with precision on demand, where if more accuracy is required, more computational time and power can be allocated. The SoC chiplet architecture has been extensively simulated and validated using state of the art CAD methodology, and has been submitted to fabrication in a dedicated 55nm GF CMOS technology wafer run. Experimental results from fabricated test chips in the same technology are also presented