Compute-and-Forward Relay Networks with Asynchronous, Mobile, and Delay-Sensitive Users

We consider a wireless network consisting of multiple source nodes, a set of relays and a destination node. Suppose the sources transmit their messages simultaneously to the relays and the destination aims to decode all the messages. At the physical layer, a conventional approach would be for the relay to decode the individual message one at a time while treating rest of the messages as interference. Compute-and-forward is a novel strategy which attempts to turn the situation around by treating the interference as a constructive phenomenon. In compute-and-forward, each relay attempts to directly compute a combination of the transmitted messages and then forwards it to the destination. Upon receiving the combinations of messages from the relays, the destination can recover all the messages by solving the received equations. When identical lattice codes are employed at the sources, error correction to integer combination of messages is a viable option by exploiting the algebraic structure of lattice codes. Therefore, compute-and-forward with lattice codes enables the relay to manage interference and perform error correction concurrently. It is shown that compute-and-forward exhibits substantial improvement in the achievable rate compared with other state-of-the-art schemes for medium to high signal-to-noise ratio regime. Despite several results that show the excellent performance of compute-and-forward, there are still important challenges to overcome before we can utilize compute-and- forward in practice. Some important challenges include the assumptions of \perfect timing synchronization "and \quasi-static fading", since these assumptions rarely hold in realistic wireless channels. So far, there are no conclusive answers to whether compute-and-forward can still provide substantial gains even when these assumptions are removed. When lattice codewords are misaligned and mixed up, decoding integer combination of messages is not straightforward since the linearity of lattice codes is generally not invariant to time shift. When channel exhibits time selectivity, it brings challenges to compute-and-forward since the linearity of lattice codes does not suit the time varying nature of the channel. Another challenge comes from the emerging technologies for future 5G communication, e.g., autonomous driving and virtual reality, where low-latency communication with high reliability is necessary. In this regard, powerful short channel codes with reasonable encoding/decoding complexity are indispensable. Although there are fruitful results on designing short channel codes for point-to-point communication, studies on short code design specifically for compute-and-forward are rarely found. The objective of this dissertation is threefold. First, we study compute-and-forward with timing-asynchronous users. Second, we consider the problem of compute-and- forward over block-fading channels. Finally, the problem of compute-and-forward for low-latency communication is studied. Throughout the dissertation, the research methods and proposed remedies will center around the design of lattice codes in order to facilitate the use of compute-and-forward in the presence of these challenges

NASA Tech Briefs, April 2011

Topics covered include: Amperometric Solid Electrolyte Oxygen Microsensors with Easy Batch Fabrication; Two-Axis Direct Fluid Shear Stress Sensor for Aerodynamic Applications; Target Assembly to Check Boresight Alignment of Active Sensors; Virtual Sensor Test Instrumentation; Evaluation of the Reflection Coefficient of Microstrip Elements for Reflectarray Antennas; Miniaturized Ka-Band Dual-Channel Radar; Continuous-Integration Laser Energy Lidar Monitor; Miniaturized Airborne Imaging Central Server System; Radiation-Tolerant, SpaceWire-Compatible Switching Fabric; Small Microprocessor for ASIC or FPGA Implementation; Source-Coupled, N-Channel, JFET-Based Digital Logic Gate Structure Using Resistive Level Shifters; High-Voltage-Input Level Translator Using Standard CMOS; Monitoring Digital Closed-Loop Feedback Systems; MASCOT - MATLAB Stability and Control Toolbox; MIRO Continuum Calibration for Asteroid Mode; GOATS Image Projection Component; Coded Modulation in C and MATLAB; Low-Dead-Volume Inlet for Vacuum Chamber; Thermal Control Method for High-Current Wire Bundles by Injecting a Thermally Conductive Filler; Method for Selective Cleaning of Mold Release from Composite Honeycomb Surfaces; Infrared-Bolometer Arrays with Reflective Backshorts; Commercialization of LARC (trade mark) -SI Polyimide Technology; Novel Low-Density Ablators Containing Hyperbranched Poly(azomethine)s; Carbon Nanotubes on Titanium Substrates for Stray Light Suppression; Monolithic, High-Speed Fiber-Optic Switching Array for Lidar; Grid-Tied Photovoltaic Power System; Spectroelectrochemical Instrument Measures TOC; A Miniaturized Video System for Monitoring Drosophila Behavior; Hydrofocusing Bioreactor Produces Anti-Cancer Alkaloids; Creep Measurement Video Extensometer; Radius of Curvature Measurement of Large Optics Using Interferometry and Laser Tracker n-B-pi-p Superlattice Infrared Detector; Safe Onboard Guidance and Control Under Probabilistic Uncertainty; General Tool for Evaluating High-Contrast Coronagraphic Telescope Performance Error Budgets; Hidden Statistics of Schroedinger Equation; Optimal Padding for the Two-Dimensional Fast Fourier Transform; Spatial Query for Planetary Data; Higher Order Mode Coupling in Feed Waveguide of a Planar Slot Array Antenna; Evolutionary Computational Methods for Identifying Emergent Behavior in Autonomous Systems; Sampling Theorem in Terms of the Bandwidth and Sampling Interval; Meteoroid/Orbital Debris Shield Engineering Development Practice and Procedure; Self-Balancing, Optical-Center-Pivot, Fast-Steering Mirror; Wireless Orbiter Hang-Angle Inclinometer System; and Internal Electrostatic Discharge Monitor - IESDM

VLSI decoding architectures: flexibility, robustness and performance

Stemming from previous studies on flexible LDPC decoders, this thesis work has been mainly focused on the development of flexible turbo and LDPC decoder designs, and on the narrowing of the power, area and speed gap they might present with respect to dedicated solutions. Additional studies have been carried out within the field of increased code performance and of decoder resiliency to hardware errors. The first chapter regroups several main contributions in the design and implementation of flexible channel decoders. The first part concerns the design of a Network-on-Chip (NoC) serving as an interconnection network for a partially parallel LDPC decoder. A best-fit NoC architecture is designed and a complete multi-standard turbo/LDPC decoder is designed and implemented. Every time the code is changed, the decoder must be reconfigured. A number of variables influence the duration of the reconfiguration process, starting from the involved codes down to decoder design choices. These are taken in account in the flexible decoder designed, and novel traffic reduction and optimization methods are then implemented. In the second chapter a study on the early stopping of iterations for LDPC decoders is presented. The energy expenditure of any LDPC decoder is directly linked to the iterative nature of the decoding algorithm. We propose an innovative multi-standard early stopping criterion for LDPC decoders that observes the evolution of simple metrics and relies on on-the-fly threshold computation. Its effectiveness is evaluated against existing techniques both in terms of saved iterations and, after implementation, in terms of actual energy saving. The third chapter portrays a study on the resilience of LDPC decoders under the effect of memory errors. Given that the purpose of channel decoders is to correct errors, LDPC decoders are intrinsically characterized by a certain degree of resistance to hardware faults. This characteristic, together with the soft nature of the stored values, results in LDPC decoders being affected differently according to the meaning of the wrong bits: ad-hoc error protection techniques, like the Unequal Error Protection devised in this chapter, can consequently be applied to different bits according to their significance. In the fourth chapter the serial concatenation of LDPC and turbo codes is presented. The concatenated FEC targets very high error correction capabilities, joining the performance of turbo codes at low SNR with that of LDPC codes at high SNR, and outperforming both current deep-space FEC schemes and concatenation-based FECs. A unified decoder for the concatenated scheme is subsequently propose