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MADX: Memristors-As-Drivers for Crossbar logic
Memristors have the potential to not only replace conventional memory, but also to open up new design possibilities because they store 1s and 0s as resistances rather than voltages. A memristor architecture that has attracted interest for its versatility and ease of integration with existing CMOS technologies is the crossbar array. In this paper, I modify the MAD scheme to create the MADX scheme for performing basic logic operations within a crossbar array. Then, I compare this scheme against two of the most well-known schemes, MAGIC and IMPLY. In the case study of a full-adder, both a one-bit and an 8-bit version, the MADX scheme achieves lower latency and substantially lower area requirements than both MAGIC and IMPLY. This is because it is more flexible about storing output values than either, does not destroy input values unlike IMPLY, and has more basic operations. In particular, it has XOR, which neither IMPLY nor MAGIC have and is useful for additionPlan II Honors Progra
Memcapacitive Devices in Logic and Crossbar Applications
Over the last decade, memristive devices have been widely adopted in
computing for various conventional and unconventional applications. While the
integration density, memory property, and nonlinear characteristics have many
benefits, reducing the energy consumption is limited by the resistive nature of
the devices. Memcapacitors would address that limitation while still having all
the benefits of memristors. Recent work has shown that with adjusted parameters
during the fabrication process, a metal-oxide device can indeed exhibit a
memcapacitive behavior. We introduce novel memcapacitive logic gates and
memcapacitive crossbar classifiers as a proof of concept that such applications
can outperform memristor-based architectures. The results illustrate that,
compared to memristive logic gates, our memcapacitive gates consume about 7x
less power. The memcapacitive crossbar classifier achieves similar
classification performance but reduces the power consumption by a factor of
about 1,500x for the MNIST dataset and a factor of about 1,000x for the
CIFAR-10 dataset compared to a memristive crossbar. Our simulation results
demonstrate that memcapacitive devices have great potential for both Boolean
logic and analog low-power applications
A CMOS Spiking Neuron for Dense Memristor-Synapse Connectivity for Brain-Inspired Computing
Neuromorphic systems that densely integrate CMOS spiking neurons and
nano-scale memristor synapses open a new avenue of brain-inspired computing.
Existing silicon neurons have molded neural biophysical dynamics but are
incompatible with memristor synapses, or used extra training circuitry thus
eliminating much of the density advantages gained by using memristors, or were
energy inefficient. Here we describe a novel CMOS spiking leaky
integrate-and-fire neuron circuit. Building on a reconfigurable architecture
with a single opamp, the described neuron accommodates a large number of
memristor synapses, and enables online spike timing dependent plasticity (STDP)
learning with optimized power consumption. Simulation results of an 180nm CMOS
design showed 97% power efficiency metric when realizing STDP learning in
10,000 memristor synapses with a nominal 1M{\Omega} memristance, and only
13{\mu}A current consumption when integrating input spikes. Therefore, the
described CMOS neuron contributes a generalized building block for large-scale
brain-inspired neuromorphic systems.Comment: This is a preprint of an article accepted for publication in
International Joint Conference on Neural Networks (IJCNN) 201
Homogeneous Spiking Neuromorphic System for Real-World Pattern Recognition
A neuromorphic chip that combines CMOS analog spiking neurons and memristive
synapses offers a promising solution to brain-inspired computing, as it can
provide massive neural network parallelism and density. Previous hybrid analog
CMOS-memristor approaches required extensive CMOS circuitry for training, and
thus eliminated most of the density advantages gained by the adoption of
memristor synapses. Further, they used different waveforms for pre and
post-synaptic spikes that added undesirable circuit overhead. Here we describe
a hardware architecture that can feature a large number of memristor synapses
to learn real-world patterns. We present a versatile CMOS neuron that combines
integrate-and-fire behavior, drives passive memristors and implements
competitive learning in a compact circuit module, and enables in-situ
plasticity in the memristor synapses. We demonstrate handwritten-digits
recognition using the proposed architecture using transistor-level circuit
simulations. As the described neuromorphic architecture is homogeneous, it
realizes a fundamental building block for large-scale energy-efficient
brain-inspired silicon chips that could lead to next-generation cognitive
computing.Comment: This is a preprint of an article accepted for publication in IEEE
Journal on Emerging and Selected Topics in Circuits and Systems, vol 5, no.
2, June 201
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