NONLINEARITY COMPENSATION AND ACCURACY IMPROVEMENT METHOD FOR AN OPTICAL ROTARY ENCODER

This paper presents a method for the nonlinearity compensation of an optical rotary encoder. The proposed method is based on the application of 1) a special 4-bit mixed analog-digital circuit used for the generation of a quasi-linear signal, and 2) a two-stage nonlinear ADC which performs linearization and digital conversion of the quasi-linear signal at the same time. The quasi-linear signal is obtained by combining fragments of phase-shifted sinusoidal signals, where each fragment is presented with a 4-bit digital code. In the continuation, the quasi-linear signal is linearized with the two-stage nonlinear ADC of a compact design based on the application of a single flash ADC in both conversion stages. Additionally, the design of the flash ADC is modified so that the number of employed comparators is equal to the resolution of the flash ADC. For instance, by linearizing an optical rotary encoder using the 4-bit mixed analog-digital circuit and the 20-bit two-stage nonlinear ADC containing 10 comparators, the maximal value of the absolute measurement error can be reduced to 3.23·10-5°

Phase ambiguity resolution for offset QPSK modulation systems

A demodulator for Offset Quaternary Phase Shift Keyed (OQPSK) signals modulated with two words resolves eight possible combinations of phase ambiguity which may produce data error by first processing received I(sub R) and Q(sub R) data in an integrated carrier loop/symbol synchronizer using a digital Costas loop with matched filters for correcting four of eight possible phase lock errors, and then the remaining four using a phase ambiguity resolver which detects the words to not only reverse the received I(sub R) and Q(sub R) data channels, but to also invert (complement) the I(sub R) and/or Q(sub R) data, or to at least complement the I(sub R) and Q(sub R) data for systems using nontransparent codes that do not have rotation direction ambiguity

Speed Error Mitigation for a DSP-Based Resolver-to-Digital Converter Using Auto-Tuning Filters

Modern resolver-to-digital converters (RDC) are typically implemented using DSP techniques to reduce hardware footprint and enhanced system accuracy. However, in such implementations, both resolver sensor and ADC channel unbalances introduce significant errors particularly in the speed output of the tracking loop. The frequency spectrum of the output error is variable depending on the resolver mechanical velocity. This paper presents the design of an auto-tuning output filter based on the interpolation of pre-computed filters for a DSP-based RDC with a type-II tracking loop. A fourth-order peak and a second-order high pass filter are designed and tested for an experimental RDC. The experimental results demonstrate significant reduction of the peak-to-peak error in the estimated speed

Digital to synchro converter

A digital-to-synchro converter is provided where a binary input code specifies a desired shaft angle and where an resolver type position transducer is employed with additional circuitry to generate a shaft position error signal indicative of the angular difference between the desired shaft angle and the actual shaft angle. The additional circuitry corrects for known and calculated errors in the shaft position detection process and equipment

A PMSM current controller system on FPGA platform

Permanent magnet synchronous motor (PMSM) has gained more interest recently in industrial applications. Digital hardware solutions such as field programmable gate arrays (FPGAs) are the most preferred methods for controlling PMSM drivers. This paper presents an implementation of a current control system for PMSM based on FPGA. Encoder-based speed and position detection method has been used in proposed hardware. The whole system has been modeled and simulated in system level using MATLAB/SIMULINK. Hardware architecture for all computational blocks is implemented using Verilog HDL. The hardware architecture has been successfully synthesized and implemented on Altera Cyclone II FPGA. Proposed system architecture and computational blocks are described and system level and RTL simulation results are presented. Simulation results show that the total computation cycle time of implemented system on Altera Cyclone II FPGA is 456ns.Keywords: PMSM, FPGA, Incremental encoder, CORDIC, Hysteresis Current Control