A built-in self-test technique for high speed analog-to-digital converters

Fundação para a Ciência e a Tecnologia (FCT) - PhD grant (SFRH/BD/62568/2009

Alternative Methods for Non-Linearity Estimation in High-Resolution Analog-to-Digital Converters

The evaluation of the linearity performance of a high resolution Analog-to- Digital Converter (ADC) by the Standard Histogram method is an outstanding challenge due to the requirement of high purity of the input signal and the high number of output data that must be acquired to obtain an acceptable accuracy on the estimation. These requirements become major application drawbacks when the measures have to be performed multiple times within long test flows and for many parts, and under an industrial environment that seeks to reduce costs and lead times as is the case in the New Space sector. This thesis introduces two alternative methods that succeed in relaxing the two previous requirements for the estimation of the Integral Nonlinearity (INL) parameter in ADCs. The methods have been evaluated by estimating the Integral Non-Linearity pattern by simulation using realistic high-resolution ADC models and experimentally by applying them to real high performance ADCs. First, the challenge of applying the Standard Histogram method for the evaluation of static parameters in high resolution ADCs and how the drawbacks are accentuated in the New Space industry is analysed, being a highly expensive method for an industrial environment where cost and lead time reduction is demanded. Several alternative methods to the Standard Histogram for estimating Integral Nonlinearity in high resolution ADCs are reviewed and studied. As the number of existing works in the literature is very large and addressing all of them is a challenge in itself, only those most relevant to the development of this thesis have been included. Methods based on spectral processing to reduce the number of data acquired for the linearity test and methods based on a double histogram to be able to use generators that do not meet the the purity requirement against the ADC to be tested are further analysed. Two novel contributions are presented in this work for the estimation of the Integral Nonlinearity in ADCs, as possible alternatives to the Standard Histogram method. The first method, referred to as SSA (Simple Spectral Approach), seeks to reduce the number of output data that need to be acquired and focuses on INL estimation using an algorithm based on processing the spectrum of the output signal when a sinusoidal input stimulus is used. This type of approach requires a much smaller number of samples than the Standard Histogram method, although the estimation accuracy will depend on how smooth or abrupt the ADC nonlinearity pattern is. In general, this algorithm cannot be used to perform a calibration of the ADC nonlinearity error, but it can be applied to find out between which limits it lies and what its approximate shape is. The second method, named SDH (Simplified Double Histogram)aims to estimate the Non-Linearity of the ADC using a poor linearity generator. The approach uses two histograms constructed from the two set of output data in response to two identical input signals except for a dc offset between them. Using a simple adder model, an extended approach named ESDH (Extended Simplified Double Histogram) addresses and corrects for possible time drifts during the two data acquisitions, so that it can be successfully applied in a non-stationary test environment. According to the experimental results obtained, the proposed algorithm achieves high estimation accuracy. Both contributions have been successfully tested in high-resolution ADCs with both simulated and real laboratory experiments, the latter using a commercial ADC with 14-bit resolution and 65Msps sampling rate (AD6644 from Analog Devices).La medida de la característica de linealidad de un convertidor analógicodigital (ADC) de alta resolución mediante el método estándar del Histograma constituye un gran desafío debido los requisitos de alta pureza de la señal de entrada y del elevado número de datos de salida que deben adquirirse para obtener una precisión aceptable en la estimación. Estos requisitos encuentran importantes inconvenientes para su aplicación cuando las medidas deben realizarse dentro de largos flujos de pruebas, múltiples veces y en un gran número de piezas, y todo bajo un entorno industrial que busca reducir costes y plazos de entrega como es el caso del sector del Nuevo Espacio. Esta tesis introduce dos métodos alternativos que consiguen relajar los dos requisitos anteriores para la estimación de los parámetros de no linealidad en los ADCs. Los métodos se han evaluado estimando el patrón de No Linealidad Integral (INL) mediante simulación utilizando modelos realistas de ADC de alta resolución y experimentalmente aplicándolos en ADCs reales. Inicialmente se analiza el reto que supone la aplicación del método estándar del Histograma para la evaluación de los parámetros estáticos en ADCs de alta resolución y cómo sus inconvenientes se acentúan en la industria del Nuevo Espacio, siendo un método altamente costoso para un entorno industrial donde se exige la reducción de costes y plazos de entrega. Se estudian métodos alternativos al Histograma estándar para la estimación de la No Linealidad Integral en ADCs de alta resolución. Como el número de trabajos es muy amplio y abordarlos todos es ya en sí un desafío, se han incluido aquellos más relevantes para el desarrollo de esta tesis. Se analizan especialmente los métodos basados en el procesamiento espectral para reducir el número de datos que necesitan ser adquiridos y los métodos basados en un doble histograma para poder utilizar generadores que no cumplen el requisito de precisión frente al ADC a medir. En este trabajo se presentan dos novedosas aportaciones para la estimación de la No Linealidad Integral en ADCs, como posibles alternativas al método estándar del Histograma. El primer método, denominado SSA (Simple Spectral Approach), busca reducir el número de datos de salida que es necesario adquirir y se centra en la estimación de la INL mediante un algoritmo basado en el procesamiento del espectro de la señal de salida cuando se utiliza un estímulo de entrada sinusoidal. Este tipo de enfoque requiere un número mucho menor de muestras que el método estándar del Histograma, aunque la precisión de la estimación dependerá de lo suave o abrupto que sea el patrón de no-linealidad del ADC a medir. En general, este algoritmo no puede utilizarse para realizar una calibración del error de no linealidad del ADC, pero puede aplicarse para averiguar entre qué límites se encuentra y cuál es su forma aproximada. El segundo método, denominado SDH (Simplified Double Histogram) tiene como objetivo estimar la no linealidad del ADC utilizando un generador de baja pureza. El algoritmo utiliza dos histogramas, construidos a partir de dos conjuntos de datos de salida en respuesta a dos señales de entrada idénticas, excepto por un desplazamiento constante entre ellas. Utilizando un modelo simple de sumador, un enfoque ampliado denominado ESDH (Extended Simplified Double Histogram) aborda y corrige las posibles derivas temporales durante las dos adquisiciones de datos, de modo que puede aplicarse con éxito en un entorno de prueba no estacionario. De acuerdo con los resultados experimentales obtenidos, el algoritmo propuesto alcanza una alta precisión de estimación. Ambas contribuciones han sido probadas en ADCs de alta resolución con experimentos tanto simulados como reales en laboratorio, estos últimos utilizando un ADC comercial con una resolución de 14 bits y una tasa de muestreo de 65Msps (AD6644 de Analog Devices)

Enabling low cost test and tuning of difficult-to-measure device specifications: application to DC-DC converters and high speed devices

Low-cost test and tuning methods for difficult-to-measure specifications are presented in this research from the following perspectives: 1)"Safe" test and self-tuning for power converters: To avoid the risk of device under test (DUT) damage during conventional load/line regulation measurement on power converter, a "safe" alternate test structure is developed where the power converter (boost/buck converter) is placed in a different mode of operation during alternative test (light switching load) as opposed to standard test (heavy switching load) to prevent damage to the DUT during manufacturing test. Based on the alternative test structure, self-tuning methods for both boost and buck converters are also developed in this thesis. In addition, to make these test structures suitable for on-chip built-in self-test (BIST) application, a special sensing circuit has been designed and implemented. Stability analysis filters and appropriate models are also implemented to predict the DUT’s electrical stability condition during test and to further predict the values of tuning knobs needed for the tuning process. 2) High bandwidth RF signal generation: Up-convertion has been widely used in high frequency RF signal generation but mixer nonlinearity results in signal distortion that is difficult to eliminate with such methods. To address this problem, a framework for low-cost high-fidelity wideband RF signal generation is developed in this thesis. Depending on the band-limited target waveform, the input data for two interleaved DACs (digital-to-analog converters) system is optimized by a matrix-model-based algorithm in such a way that it minimizes the distortion between one of its image replicas in the frequency domain and the target RF waveform within a specified signal bandwidth. The approach is used to demonstrate how interferers with specified frequency characteristics can be synthesized at low cost for interference testing of RF communications systems. The frameworks presented in this thesis have a significant impact in enabling low-cost test and tuning of difficult-to-measure device specifications for power converter and high-speed devices.Ph.D

Reduced-complexity Digital Predistortion in Flexible Radio Spectrum Access

Wireless communications is nowadays seen as one of the main foundations of technological advancements in, e.g., healthcare, education, agriculture, transportation, computing, personal communications, media, and entertainment. This requires major technological developments and advances at different levels of the wireless communication systems and networks. In particular, it is required to utilize the currently available frequency spectrum in a more and more efficient way, while also adopting new spectral bands. Moreover, it is required that cheaper and smaller electronic components are used to build future wireless communication systems to facilitate increasingly cost-effective solutions. Meanwhile, energy efficiency becomes extremely important in wide scale deployments of the networks both from a running cost point of view, and from an environmental impact point of view. This is the big picture, or the so called ‘bird’s eye view’ of the challenges that are yet to be met in this very interesting and fast developing field of science.The power amplifier (PA) is the most power-hungry component in most RF transmitters. Consequently, its energy efficiency significantly contributes to the overall energy efficiency of the transmitter, and in fact the whole wireless network. Unfortunately, energy efficiency enhancement implies operating the PA closer to its saturation region, which typically results in severe nonlinear distortion that can deteriorate the signal quality and cause interference to neighboring users, both of which negatively impact the system spectral efficiency. Moreover, in flexible spectrum access scenarios, which are essential for improving the spectral efficiency, particular in the form of non-contiguous radio spectrum access, the nonlinear distortion due to the PA becomes even more severe and can significantly impact the overall network performance. For example, in noncontiguous carrier aggregation (CA) in LTE-Advanced, it has been demonstrated that in addition to the classical in-band distortion and regrowth around the main carriers, harmful spurious emission components are generated which can easily violate the spurious emission limits even in the case of user equipment (UE) transmitters.Technological advances in the digital electronics domain have enabled us to approach this problem from a digital signal processing point of view in the form of widely-adopted and researched digital predistortion (DPD) technology. However, when the signal bandwidth gets larger, and flexible or non-contiguous spectrum access is introduced, the complexity of the DPD increases and the power consumed in the digital domain by the DPD itself becomes higher and higher, to the extent that it might be close to, or even surpass, the energy savings achieved from using a more efficient PA. The problem becomes even more challenging at the UE side which has relatively limited computational capabilities and lower transmit power. This dilemma can be resolved by developing novel reduced-complexity DPD solutions in such flexible spectrum access and/or wide bandwidth scenarios while not sacrificing the DPD performance, which is the main topic area that this thesis work contributes to.The first contribution of this thesis is the development of a spur-injection based sub-band DPD structure for spurious emission mitigation in noncontiguous transmission scenarios. A novel and effective learning algorithm is also introduced, for the proposed sub-band DPD, based on the decorrelation principle. Mathematical models of the unwanted emissions are formulated based on realistic PA models with memory, followed by developing an efficient DPD structure for mitigating these emissions with reducedcomplexity in both the DPD main processing and learning paths while providing excellent spurious emission suppression. In the special case when the spurious emissions overlap with the own RX band in frequency division duplexing (FDD) transceivers, a novel subband DPD solution is also developed that uses the main RX for DPD learning without requiring any additional observation RX, thus further reducing the DPD complexity.The second contribution is the development of a novel reduced-complexity concurrent DPD, with a single-feedback receiver path, for carrier aggregation-like scenarios. The proposed solution is based on a simple and flexible DPD structure with decorrelationbased parameter learning. Practical simulations and RF measurements demonstrate that the proposed concurrent DPD provides excellent linearization performance, in terms of in-band error vector magnitude (EVM) and adjacent channel leakage ratio (ACLR), when compared to state-of-the-art concurrent DPD solutions, despite its reduced computational complexity in both the DPD main path processing and parameter learning.The third contribution is the development of a new and novel frequency-optimized DPD solution which can tailor its linearization capabilities to any particular regions of the spectrum. Detailed mathematical expressions of the power spectrum at the PA output as a function of the DPD coefficients are formulated. A Newton-Raphson optimization routine is then utilized to optimize the suppression of unwanted emissions at arbitrary pre-specified frequencies at the PA output. From a complexity reduction perspective, this means that for a given linearization performance at a particular frequency range, an optimized and reduced-complexity DPD can be used.Detailed quantitative complexity analysis, of all the proposed DPD solutions, is performed in this thesis. The complexity and linearization performance are also compared to state-of-the-art DPD solutions in the literature to validate and demonstrate the complexity reduction aspect without sacrificing the linearization performance. Moreover, all the DPD solutions developed in this thesis are tested in practical RF environments using real cellular power amplifiers that are commercially used in the latest wireless communication systems, both at the base station side and at the mobile terminal side. These experiments, along with the strong theoretical foundation of the developed DPD solutions prove that they can be commercially used as such to enhance the performance, energy efficiency, and cost effectiveness of next generation wireless transmitters

Direct digital synthesizers : theory, design and applications

Traditional designs of high bandwidth frequency synthesizers employ the use of a phase-locked-loop (PLL). A direct digital synthesizer (DDS) provides many significant advantages over the PLL approaches. Fast settling time, sub-Hertz frequency resolution, continuous-phase switching response and low phase noise are features easily obtainable in the DDS systems. Although the principle of the DDS has been known for many years, the DDS did not play a dominant role in wideband frequency generation until recent years. Earlier DDSs were limited to produce narrow bands of closely spaced frequencies, due to limitations of digital logic and D/A-converter technologies. Recent advantages in integrated circuit (IC) technologies have brought about remarkable progress in this area. By programming the DDS, adaptive channel bandwidths, modulation formats, frequency hopping and data rates are easily achieved. This is an important step towards a "software-radio" which can be used in various systems. The DDS could be applied in the modulator or demodulator in the communication systems. The applications of DDS are restricted to the modulator in the base station. The aim of this research was to find an optimal front-end for a transmitter by focusing on the circuit implementations of the DDS, but the research also includes the interface to baseband circuitry and system level design aspects of digital communication systems. The theoretical analysis gives an overview of the functioning of DDS, especially with respect to noise and spurs. Different spur reduction techniques are studied in detail. Four ICs, which were the circuit implementations of the DDS, were designed. One programmable logic device implementation of the CORDIC based quadrature amplitude modulation (QAM) modulator was designed with a separate D/A converter IC. For the realization of these designs some new building blocks, e.g. a new tunable error feedback structure and a novel and more cost-effective digital power ramp generator, were developed.reviewe