1,857 research outputs found
Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocessors
Thanks to aggressive scaling of transistor dimensions, computers have revolutionized our life. However, the increasing unreliability of devices fabricated in nanoscale technologies emerged as a major threat for the future success of computers. In particular, accelerated transistor aging is of great importance, as it reduces the lifetime of digital systems. This thesis addresses this challenge by proposing new methods to model, analyze and mitigate aging at microarchitecture-level and above
VLSI implementation of a multi-mode turbo/LDPC decoder architecture
Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel contributions of this paper are: i) tackling the reconfiguration issue introducing a formal and systematic treatment that, to the best of our knowledge, was not previously addressed; ii) proposing a reconfigurable NoCbased turbo/LDPC decoder architecture and showing that wide flexibility can be achieved with a small complexity overhead. Obtained results show that dynamic switching between most of considered communication standards is possible without pausing the decoding activity. Moreover, post-layout results show that tailoring the proposed architecture to the WiMAX standard leads to an area occupation of 2.75 mm2 and a power consumption of 101.5 mW in the worst case
Reconfigurable writing architecture for reliable RRAM operation in wide temperature ranges
Resistive switching memories [resistive RAM (RRAM)] are an attractive alternative to nonvolatile storage and nonconventional computing systems, but their behavior strongly depends on the cell features, driver circuit, and working conditions. In particular, the circuit temperature and writing voltage schemes become critical issues, determining resistive switching memories performance. These dependencies usually force a design time tradeoff among reliability, device endurance, and power consumption, thereby imposing nonflexible functioning schemes and limiting the system performance. In this paper, we present a writing architecture that ensures the correct operation no matter the working temperature and allows the dynamic load of application-oriented writing profiles. Thus, taking advantage of more efficient configurations, the system can be dynamically adapted to overcome RRAM intrinsic challenges. Several profiles are analyzed regarding power consumption, temperature-variations protection, and operation speed, showing speedups near 700x compared with other published drivers
High-Performance Energy-Efficient and Reliable Design of Spin-Transfer Torque Magnetic Memory
In this dissertation new computing paradigms, architectures and design philosophy are proposed and evaluated for adopting the STT-MRAM technology as highly reliable, energy efficient and fast memory. For this purpose, a novel cross-layer framework from the cell-level all the way up to the system- and application-level has been developed. In these framework, the reliability issues are modeled accurately with appropriate fault models at different abstraction levels in order to analyze the overall failure rates of the entire memory and its Mean Time To Failure (MTTF) along with considering the temperature and process variation effects. Design-time, compile-time and run-time solutions have been provided to address the challenges associated with STT-MRAM. The effectiveness of the proposed solutions is demonstrated in extensive experiments that show significant improvements in comparison to state-of-the-art solutions, i.e. lower-power, higher-performance and more reliable STT-MRAM design
A High-Performance and Low-Complexity 5G LDPC Decoder: Algorithm and Implementation
5G New Radio (NR) has stringent demands on both performance and complexity
for the design of low-density parity-check (LDPC) decoding algorithms and
corresponding VLSI implementations. Furthermore, decoders must fully support
the wide range of all 5G NR blocklengths and code rates, which is a significant
challenge. In this paper, we present a high-performance and low-complexity LDPC
decoder, tailor-made to fulfill the 5G requirements. First, to close the gap
between belief propagation (BP) decoding and its approximations in hardware, we
propose an extension of adjusted min-sum decoding, called generalized adjusted
min-sum (GA-MS) decoding. This decoding algorithm flexibly truncates the
incoming messages at the check node level and carefully approximates the
non-linear functions of BP decoding to balance the error-rate and hardware
complexity. Numerical results demonstrate that the proposed fixed-point GAMS
has only a minor gap of 0.1 dB compared to floating-point BP under various
scenarios of 5G standard specifications. Secondly, we present a fully
reconfigurable 5G NR LDPC decoder implementation based on GA-MS decoding. Given
that memory occupies a substantial portion of the decoder area, we adopt
multiple data compression and approximation techniques to reduce 42.2% of the
memory overhead. The corresponding 28nm FD-SOI ASIC decoder has a core area of
1.823 mm2 and operates at 895 MHz. It is compatible with all 5G NR LDPC codes
and achieves a peak throughput of 24.42 Gbps and a maximum area efficiency of
13.40 Gbps/mm2 at 4 decoding iterations.Comment: 14 pages, 14 figure
Engineering study for a mass memory system for advanced spacecrafts Final report, 1 Dec. 1969 - 1 Jul. 1970
Mass memory system for advanced spacecraf
- …