Channel coded iterative center-shifting K-best sphere detection for rank-deficient systems

Based on an EXtrinsic Information Transfer (EXIT) chart assisted receiver design, a low-complexity near-Maximum A Posteriori (MAP) detector is constructed for high-throughput MIMO systems. A high throughput is achieved by invoking high-order modulation schemes and/or multiple transmit antennas, while employing a novel sphere detector (SD) termed as a center-shifting SD scheme, which updates the SD’s search center during its consecutive iterations with the aid of channel decoder. Two low-complexity iterative center-shifting SD aided receiver architectures are investigated, namely the direct-hard-decision centershifting (DHDC) and the direct-soft-decision center-shifting (DSDC) schemes. Both of them are capable of attaining a considerable memory and complexity reduction over the conventional SD-aided iterative benchmark receiver. For example, the DSDC scheme reduces the candidate-list-generation-related and extrinsic-LLR-calculation related complexity by a factor of 3.5 and 16, respectively. As a further benefit, the associated memory requirements were also reduced by a factor of 16

An Iterative Soft Decision Based LR-Aided MIMO Detector

The demand for wireless and high-rate communication system is increasing gradually and multiple-input-multiple-output (MIMO) is one of the feasible solutions to accommodate the growing demand for its spatial multiplexing and diversity gain. However, with high number of antennas, the computational and hardware complexity of MIMO increases exponentially. This accumulating complexity is a paramount problem in MIMO detection system directly leading to large power consumption. Hence, the major focus of this dissertation is algorithmic and hardware development of MIMO decoder with reduced complexity for both real and complex domain, which can be a beneficial solution with power efficiency and high throughput. Both hard and soft domain MIMO detectors are considered. The use of lattice reduction (LR) algorithm and on-demand-child-expansion for the reduction of noise propagation and node calculation respectively are the two of the key features of our developed architecture, presented in this literature. The real domain iterative soft MIMO decoding algorithm, simulated for 4 × 4 MIMO with different modulation scheme, achieves 1.1 to 2.7 dB improvement over Lease Sphere Decoder (LSD) and more than 8x reduction in list size, K as well as complexity of the detector. Next, the iterative real domain K-Best decoder is expanded to the complex domain with new detection scheme. It attains 6.9 to 8.0 dB improvement over real domain K-Best decoder and 1.4 to 2.5 dB better performance over conventional complex decoder for 8 × 8 MIMO with 64 QAM modulation scheme. Besides K, a new adjustable parameter, Rlimit has been introduced in order to append re-configurability trading-off between complexity and performance. After that, a novel low-power hardware architecture of complex decoder is developed for 8 × 8 MIMO and 64 QAM modulation scheme. The total word length of only 16 bits has been adopted limiting the bit error rate (BER) degradation to 0.3 dB with K and Rlimit equal to 4. The proposed VLSI architecture is modeled in Verilog HDL using Xilinx and synthesized using Synopsys Design Vision in 45 nm CMOS technology. According to the synthesize result, it achieves 1090.8 Mbps throughput with power consumption of 580 mW and latency of 0.33 us. The maximum frequency the design proposed is 181.8 MHz. All of the proposed decoders mentioned above are bounded by the fixed K. Hence, an adaptive real domain K-Best decoder is further developed to achieve the similar performance with less K, thereby reducing the computational complexity of the decoder. It does not require accurate SNR measurement to perform the initial estimation of list size, K. Instead, the difference between the first two minimal distances is considered, which inherently eliminates complexity. In summary, a novel iterative K-Best detector for both real and complex domain with efficient VLSI design is proposed in this dissertation. The results from extensive simulation and VHDL with analysis using Synopsys tool are also presented for justification and validation of the proposed works

An Iterative Soft Decision Based LR-Aided MIMO Detector

The demand for wireless and high-rate communication system is increasing gradually and multiple-input-multiple-output (MIMO) is one of the feasible solutions to accommodate the growing demand for its spatial multiplexing and diversity gain. However, with high number of antennas, the computational and hardware complexity of MIMO increases exponentially. This accumulating complexity is a paramount problem in MIMO detection system directly leading to large power consumption. Hence, the major focus of this dissertation is algorithmic and hardware development of MIMO decoder with reduced complexity for both real and complex domain, which can be a beneficial solution with power efficiency and high throughput. Both hard and soft domain MIMO detectors are considered. The use of lattice reduction (LR) algorithm and on-demand-child-expansion for the reduction of noise propagation and node calculation respectively are the two of the key features of our developed architecture, presented in this literature. The real domain iterative soft MIMO decoding algorithm, simulated for 4 × 4 MIMO with different modulation scheme, achieves 1.1 to 2.7 dB improvement over Lease Sphere Decoder (LSD) and more than 8x reduction in list size, K as well as complexity of the detector. Next, the iterative real domain K-Best decoder is expanded to the complex domain with new detection scheme. It attains 6.9 to 8.0 dB improvement over real domain K-Best decoder and 1.4 to 2.5 dB better performance over conventional complex decoder for 8 × 8 MIMO with 64 QAM modulation scheme. Besides K, a new adjustable parameter, Rlimit has been introduced in order to append re-configurability trading-off between complexity and performance. After that, a novel low-power hardware architecture of complex decoder is developed for 8 × 8 MIMO and 64 QAM modulation scheme. The total word length of only 16 bits has been adopted limiting the bit error rate (BER) degradation to 0.3 dB with K and Rlimit equal to 4. The proposed VLSI architecture is modeled in Verilog HDL using Xilinx and synthesized using Synopsys Design Vision in 45 nm CMOS technology. According to the synthesize result, it achieves 1090.8 Mbps throughput with power consumption of 580 mW and latency of 0.33 us. The maximum frequency the design proposed is 181.8 MHz. All of the proposed decoders mentioned above are bounded by the fixed K. Hence, an adaptive real domain K-Best decoder is further developed to achieve the similar performance with less K, thereby reducing the computational complexity of the decoder. It does not require accurate SNR measurement to perform the initial estimation of list size, K. Instead, the difference between the first two minimal distances is considered, which inherently eliminates complexity. In summary, a novel iterative K-Best detector for both real and complex domain with efficient VLSI design is proposed in this dissertation. The results from extensive simulation and VHDL with analysis using Synopsys tool are also presented for justification and validation of the proposed works

FlexCore: Massively Parallel and Flexible Processing for Large MIMO Access Points

Large MIMO base stations remain among wireless network designers’ best tools for increasing wireless throughput while serving many clients, but current system designs, sacrifice throughput with simple linear MIMO detection algorithms. Higher-performance detection techniques are known, but remain off the table because these systems parallelize their computation at the level of a whole OFDM subcarrier, sufficing only for the less demanding linear detection approaches they opt for. This paper presents FlexCore, the first computational architecture capable of parallelizing the detection of large numbers of mutually-interfering information streams at a granularity below individual OFDM subcarriers, in a nearly-embarrassingly parallel manner while utilizing any number of available processing elements. For 12 clients sending 64-QAM symbols to a 12-antenna base station, our WARP testbed evaluation shows similar network throughput to the state-of-the-art while using an order of magnitude fewer processing elements. For the same scenario, our combined WARP-GPU testbed evaluation demonstrates a 19x computational speedup, with 97% increased energy efficiency when compared with the state of the art. Finally, for the same scenario, an FPGA-based comparison between FlexCore and the state of the art shows that FlexCore can achieve up to 96% better energy efficiency, and can offer up to 32x the processing throughput

Iterative H.264 Source and Channel Decoding Using Sphere Packing Modulation Aided Layered Steered Space-Time Codes

The conventional two-stage turbo-detection schemes generally suffer from a Bit Error Rate (BER) floor. In this paper we circumvent this deficiency by proposing a three-stage turbo detected Sphere Packing (SP) modulation aided Layered Steered Space-Time Coding (LSSTC) scheme for H.264 coded video transmission over correlated Rayleigh fading channels. The soft-bit assisted H.264 coded bit-stream is protected using low-complexity short-block codes (SBCs), combined with a rate-1 recursive inner precoder is employed as an intermediate code which has an infinite impulse response and hence beneficially spreads the extrinsic information across the constituent decoders. This allows us to avoid having a BER floor. Additionally, the convergence behaviour of this serially concatenated scheme is investigated with the aid of Extrinsic Information Transfer (EXIT) Charts. The proposed system exhibits an Eb/N0 gain of about 12 dB in comparison to the benchmark scheme carrying out iterative source-channel decoding as well as Layered Steered Space-Time Coding (LSSTC) aided Sphere Packing (SP)demodulation, but dispensing with the optimised SBCs

Downlink Steered Space-Time Spreading Assisted Generalised Multicarrier DS-CDMA Using Sphere-Packing-Aided Multilevel Coding

This paper presents a novel generalised Multi-Carrier Direct Sequence Code Division Multiple Access (MC DS-CDMA) system invoking smart antennas for improving the achievable performance in the downlink, as well as employing multi-dimensional Sphere Packing (SP) modulation for increasing the achievable diversity product. In this contribution, the MC DS-CDMA transmitter considered employs multiple Antenna Arrays (AA) and each of the AAs consists of several antenna elements. Furthermore, the proposed system employs both time- and frequency- (TF) domain spreading for extending the achievable capacity, when combined with a novel user-grouping technique for reducing the effects of Multiuser Interference (MUI). Moreover, in order to further enhance the system’s performance, we invoke a MultiLevel Coding (MLC) scheme, whose component codes are determined using the so-called equivalent capacity based constituent-code rate-calculation procedure invoking a 4-dimensional bit-to-SP-symbol mapping scheme. Our results demonstrate an approximately 3.8 dB Eb/N0 gain over an identical throughput scheme dispensing with SP modulation at a BER of 10?5