Infrastructure for Detector Research and Development towards the International Linear Collider

The EUDET-project was launched to create an infrastructure for developing and testing new and advanced detector technologies to be used at a future linear collider. The aim was to make possible experimentation and analysis of data for institutes, which otherwise could not be realized due to lack of resources. The infrastructure comprised an analysis and software network, and instrumentation infrastructures for tracking detectors as well as for calorimetry.Comment: 54 pages, 48 picture

INTEGRATED SINGLE-PHOTON SENSING AND PROCESSING PLATFORM IN STANDARD CMOS

Practical implementation of large SPAD-based sensor arrays in the standard CMOS process has been fraught with challenges due to the many performance trade-offs existing at both the device and the system level [1]. At the device level the performance challenge stems from the suboptimal optical characteristics associated with the standard CMOS fabrication process. The challenge at the system level is the development of monolithic readout architecture capable of supporting the large volume of dynamic traffic, associated with multiple single-photon pixels, without limiting the dynamic range and throughput of the sensor. Due to trade-offs in both functionality and performance, no general solution currently exists for an integrated single-photon sensor in standard CMOS single photon sensing and multi-photon resolution. The research described herein is directed towards the development of a versatile high performance integrated SPAD sensor in the standard CMOS process. Towards this purpose a SPAD device with elongated junction geometry and a perimeter field gate that features a large detection area and a highly reduced dark noise has been presented and characterized. Additionally, a novel front-end system for optimizing the dynamic range and after-pulsing noise of the pixel has been developed. The pixel is also equipped with an output interface with an adjustable pulse width response. In order to further enhance the effective dynamic range of the pixel a theoretical model for accurate dead time related loss compensation has been developed and verified. This thesis also introduces a new paradigm for electrical generation and encoding of the SPAD array response that supports fully digital operation at the pixel level while enabling dynamic discrete time amplitude encoding of the array response. Thus offering a first ever system solution to simultaneously exploit both the dynamic nature and the digital profile of the SPAD response. The array interface, comprising of multiple digital inputs capacitively coupled onto a shared quasi-floating sense node, in conjunction with the integrated digital decoding and readout electronics represents the first ever solid state single-photon sensor capable of both photon counting and photon number resolution. The viability of the readout architecture is demonstrated through simulations and preliminary proof of concept measurements

Physical Aspects of VLSI Design with a Focus on Three-Dimensional Integrated Circuit Applications

This work is on three-dimensional integration (3DI), and physical problems and aspects of VLSI design. Miniaturization and highly complex integrated systems in microelectronics have led to the 3DI development as a promising technological approach. 3DI offers numerous advantages: Size, power consumption, hybrid integration etc., with more thermal problems and physical complexity as trade-offs. We open this work by presenting the design and testing of an example 3DI system, to our knowledge the first self-powering system in a three-dimensional SOI technology. The system uses ambient optical energy harvested by a photodiode array and stored in an integrated capacitor. An on-chip metal interconnect network, beyond its designed role, behaves as a parasitic load vulnerable to electromagnetic coupling. We have developed a spatially-dependent, transient Green's Function based method of calculating the response of an interconnect network to noise. This efficient method can model network delays and noise sensitivity, which are involved problems in both planar and especially in 3DICs. Three-dimensional systems are more susceptible to thermal problems, which also affect VLSI with high power densities, of complex systems and under extreme temperatures. We analytically and experimentally investigate thermal effects in ICs. We study the effects of non-uniform, non-isotropic thermal conductivity of the typically complex IC material system, with a simulator we developed including this complexity. Through our simulations, verified by experiments, we propose a method of cooling or directionally heating IC regions. 3DICs are suited for developing wireless sensor networks, commonly referred to as ``smart dust.'' The ideal smart dust node includes RF communication circuits with on-chip passive components. We present an experimental study of on-chip inductors and transformers as integrated passives. We also demonstrate the performance improvement in 3DI with its lower capacitive loads. 3DI technology is just one example of the intense development in today's electronics, which maintains the need for educational methods to assist student recruitment into technology, to prepare students for a demanding technological landscape, and to raise societal awareness of technology. We conclude this work by presenting three electrical engineering curricula we designed and implemented, targeting these needs among others

Chemical Current-Conveyor: a new approach in biochemical computation

Biochemical sensors that are low cost, small in size and compatible with integrated circuit technology play an essential part in the drive towards personalised healthcare and the research described in this thesis is concerned with this area of medical instrumentation. A new biochemical measurement system able to sense key properties of biochemical fluids is presented. This new integrated circuit biochemical sensor, called the Chemical Current-Conveyor, uses the ion sensitive field effect transistor as the input sensor combined with the current-conveyor, an analog building-block, to produce a range of measurement systems. The concept of the Chemical Current-Conveyor is presented together with the design and subsequent fabrication of a demonstrator integrated circuit built on conventional 0.35μm CMOS silicon technology. The silicon area of the Chemical Current-Conveyor is (92μm x 172μm) for the N-channel version and (99μm x 165μm) for the P-channel version. Power consumption for the N-channel version is 30μW and 43μW for the P-channel version with a full load of 1MΩ. The maximum sensitivity achieved for pH measurement was 46mV per pH. The potential of the Chemical Current Conveyor as a versatile biochemical integrated circuit, able to produce output information in an appropriate form for direct clinical use has been confirmed by applications including measurement of (i) pH, (ii) buffer index ( ), (iii) urea, (iv) creatinine and (v) urea:creatinine ratio. In all five cases the device has been demonstrated successfully, confirming the validity of the original aim of this research project, namely to produce a versatile and flexible analog circuit for many biochemical measurement applications. Finally, the thesis closes with discussion of another potential application area for the Chemical Current Conveyor and the main contributions can be summarised by the design and development of the first: ISFET based current-conveyor biochemical sensor, called 'Chemical Current Conveyor, CCCII+' has been designed and developed. It is a general purpose biochemical analog building-block for several biochemical measurements. Real-time buffer capacity measurement system, based on the CCCII+, which exploits the imbedded analog computation capability of the CCCII+. Real-time enzyme based CCCII+ namely, Creatinine-CCCII+ and Urea-CCCII+ for real-time monitoring system of renal system. The system can provide outputs of 3 important parameters of the renal system, namely (i) urea concentration, (ii) creatinine concentration, and (ii) urea to creatinine ratio

Electrophoretic deposition of ferrite

The ability to integrate a material with a high permeability on chip, allows for magnetically coupled circuits and structures to be designed and incorporated along side CMOS circuitry. Devices ranging from A.C. transformers to magnetically driven MEMS structures can be designed and fabricated. Desirable characteristics of magnetic cores for integrated inductors and transformers are first high saturation flux in order to obtain high saturation current; high permeability to obtain high inductance; high resistivity to reduce eddy current loss at high frequencies and compatible deposition and patterning processes. High frequency magnetic materials are oxide based ceramics and are therefore difficult to evaporate, sputter, plate and selectively etched. ElectroPhoretic Deposition (EPD) is a method where insulating particles are imparted charge in a suspension and are made to deposit on an electrode by applying electric field. EPD has been extensively employed in depositing oxide based phosphors for display applications. In this study, ferrite particles have been prepared by grinding sintered toroids and deposited by EPD. The electrophoretic solution bath is composed of isopropyl alcohol with traces of Mg(N03)2 and La(N03)3 salts. Glycerol is added to the solution bath as a surfactant to promote increased substrate adhesion. The dissociation of magnesium nitrate in the solution bath charges the ferrite particles. An electric field of ~ 50-160 V/cm is applied with negative terminal connected to the wafer to be plated and aluminum electrode is used as the anode. The deposition process is found to be self limiting with the initial high elerophoretic current declining to 10% of its value in 10 minutes. The deposition rate and zeta potential measurements indicate a high particle velocity on the order 5.7x10-3 cm/s with an electric field of 160V/cm generated across the 2 cm electrode spacing. Pattern filling and conformal coverage in copper damascene planar microinductors has been investigated. A method to extracted permeability from S11 impedance analysis has been employed. It has been found that grinding process deteriorates magnetic response. With recent advances in magnetic particle technology for high frequency materials, these results enable unique hard and soft powder ferrite material to be selectively deposited in wide variety of CMOS and MEM’s based applications

Technical Design Report for the PANDA Micro Vertex Detector

This document illustrates the technical layout and the expected performance of the Micro Vertex Detector (MVD) of the PANDA experiment. The MVD will detect charged particles as close as possible to the interaction zone. Design criteria and the optimisation process as well as the technical solutions chosen are discussed and the results of this process are subjected to extensive Monte Carlo physics studies. The route towards realisation of the detector is outlined

An Analog VLSI Deep Machine Learning Implementation

Machine learning systems provide automated data processing and see a wide range of applications. Direct processing of raw high-dimensional data such as images and video by machine learning systems is impractical both due to prohibitive power consumption and the “curse of dimensionality,” which makes learning tasks exponentially more difficult as dimension increases. Deep machine learning (DML) mimics the hierarchical presentation of information in the human brain to achieve robust automated feature extraction, reducing the dimension of such data. However, the computational complexity of DML systems limits large-scale implementations in standard digital computers. Custom analog signal processing (ASP) can yield much higher energy efficiency than digital signal processing (DSP), presenting means of overcoming these limitations. The purpose of this work is to develop an analog implementation of DML system. First, an analog memory is proposed as an essential component of the learning systems. It uses the charge trapped on the floating gate to store analog value in a non-volatile way. The memory is compatible with standard digital CMOS process and allows random-accessible bi-directional updates without the need for on-chip charge pump or high voltage switch. Second, architecture and circuits are developed to realize an online k-means clustering algorithm in analog signal processing. It achieves automatic recognition of underlying data pattern and online extraction of data statistical parameters. This unsupervised learning system constitutes the computation node in the deep machine learning hierarchy. Third, a 3-layer, 7-node analog deep machine learning engine is designed featuring online unsupervised trainability and non-volatile floating-gate analog storage. It utilizes massively parallel reconfigurable current-mode analog architecture to realize efficient computation. And algorithm-level feedback is leveraged to provide robustness to circuit imperfections in analog signal processing. At a processing speed of 8300 input vectors per second, it achieves 1×1012 operation per second per Watt of peak energy efficiency. In addition, an ultra-low-power tunable bump circuit is presented to provide similarity measures in analog signal processing. It incorporates a novel wide-input-range tunable pseudo-differential transconductor. The circuit demonstrates tunability of bump center, width and height with a power consumption significantly lower than previous works

Ultra-Low Power Wake Up Receiver For Medical Implant Communications Service Transceiver

This thesis explores the specific requirements and challenges for the design of a dedicated wake-up receiver for medical implant communication services equipped with a novel “uncertain-IF†architecture combined with a high – Q filtering MEMS resonator and a free running CMOS ring oscillator as the RF LO. The receiver prototype, implements an IBM 0.18μm mixed-signal 7ML RF CMOS technology and achieves a sensitivity of -62 dBm at 404MHz while consuming \u3c100 μW from a 1 V supply