22,223 research outputs found
A multiplexed mixed-signal fuzzy architecture
Analog circuits provide better area/power efficiency than their digital counterparts for low-medium precision requirements. This limit in precision as well as the lack of design tools when compared to the digital approach, imposes a limit of complexity, hence fuzzy analog controllers are usually oriented to fast low-power systems with low-medium complexity. The paper presents a strategy to preserve most of the advantages of an analog implementation, while allowing a notorious increment of the system complexity. Such strategy consists in implementing a reduced number of rules, those that really determine the output in a lattice controller, which we call analog core, then this core is dynamically programmed to perform the computation related to a specific rule set. The data to program the analog core are stored in a memory, and constitutes the whole knowledge base in a kind of virtual rule set. HSPICE simulations from an exemplary controller are shown to illustrate the viability of the proposal
Transistor-Level Synthesis of Pipeline Analog-to-Digital Converters Using a Design-Space Reduction Algorithm
A novel transistor-level synthesis procedure for pipeline ADCs is presented. This procedure is able to directly map high-level converter specifications onto transistor sizes and biasing conditions. It is based on the combination of behavioral models for performance evaluation, optimization routines to minimize the power and area consumption of the circuit solution, and an algorithm to efficiently constraint the converter design space. This algorithm precludes the cost of lengthy bottom-up verifications and speeds up the synthesis task. The approach is herein demonstrated via the design of a 0.13 ÎŒm CMOS 10 bits@60 MS/s pipeline ADC with energy consumption per conversion of only 0.54 pJ@1 MHz, making it one of the most energy-efficient 10-bit video-rate pipeline ADCs reported to date. The computational cost of this design is of only 25 min of CPU time, and includes the evaluation of 13 different pipeline architectures potentially feasible for the targeted specifications. The optimum design derived from the synthesis procedure has been fine tuned to support PVT variations, laid out together with other auxiliary blocks, and fabricated. The experimental results show a power consumption of 23 [email protected] V and an effective resolution of 9.47-bit@1 MHz. Bearing in mind that no specific power reduction strategy has been applied; the mentioned results confirm the reliability of the proposed approach.Ministerio de Ciencia e InnovaciĂłn TEC2009-08447Junta de AndalucĂa TIC-0281
Neuro-fuzzy chip to handle complex tasks with analog performance
This paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of power consumption, inputâoutput delay, and precision, performs as a fully analog implementation.
However, it has much larger complexity than its purely analog counterparts. This combination of performance and complexity is achieved through the use of a mixed-signal architecture consisting
of a programmable analog core of reduced complexity, and a strategy, and the associated mixed-signal circuitry, to cover the whole input space through the dynamic programming of this core.
Since errors and delays are proportional to the reduced number of fuzzy rules included in the analog core, they are much smaller than in the case where the whole rule set is implemented by analog circuitry. Also, the area and the power consumption of the new architecture
are smaller than those of its purely analog counterparts simply because most rules are implemented through programming.
The Paper presents a set of building blocks associated to this architecture, and gives results for an exemplary prototype.
This prototype, called multiplexing fuzzy controller (MFCON), has been realized in a CMOS 0.7 um standard technology. It has
two inputs, implements 64 rules, and features 500 ns of input to output delay with 16-mW of power consumption. Results from the chip in a control application with a dc motor are also provided
Neuro-fuzzy chip to handle complex tasks with analog performance
This Paper presents a mixed-signal neuro-fuzzy controller chip which, in terms of
power consumption, input-output delay and precision performs as a fully analog
implementation. However, it has much larger complexity than its purely analog
counterparts. This combination of performance and complexity is achieved through
the use of a mixed-signal architecture consisting of a programmable analog core of
reduced complexity, and a strategy, and the associated mixed-signal circuitry, to
cover the whole input space through the dynamic programming of this core [1].
Since errors and delays are proportional to the reduced number of fuzzy rules
included in the analog core, they are much smaller than in the case where the whole
rule set is implemented by analog circuitry. Also, the area and the power
consumption of the new architecture are smaller than those of its purely analog
counterparts simply because most rules are implemented through programming.
The Paper presents a set of building blocks associated to this architecture, and gives
results for an exemplary prototype. This prototype, called MFCON, has been
realized in a CMOS 0.7ÎŒm standard technology. It has two inputs, implements 64
rules and features 500ns of input to output delay with 16mW of power consumption.
Results from the chip in a control application with a DC motor are also provided
Quantized Feedback Control Software Synthesis from System Level Formal Specifications for Buck DC/DC Converters
Many Embedded Systems are indeed Software Based Control Systems (SBCSs), that
is control systems whose controller consists of control software running on a
microcontroller device. This motivates investigation on Formal Model Based
Design approaches for automatic synthesis of SBCS control software. In previous
works we presented an algorithm, along with a tool QKS implementing it, that
from a formal model (as a Discrete Time Linear Hybrid System, DTLHS) of the
controlled system (plant), implementation specifications (that is, number of
bits in the Analog-to-Digital, AD, conversion) and System Level Formal
Specifications (that is, safety and liveness requirements for the closed loop
system) returns correct-by-construction control software that has a Worst Case
Execution Time (WCET) linear in the number of AD bits and meets the given
specifications. In this technical report we present full experimental results
on using it to synthesize control software for two versions of buck DC-DC
converters (single-input and multi-input), a widely used mixed-mode analog
circuit.Comment: arXiv admin note: text overlap with arXiv:1107.563
Analog Circuits in Ultra-Deep-Submicron CMOS
Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena
Functionals of Brownian bridges arising in the current mismatch in D/A-converters
Digital-to-analog converters (DAC) transform signals from the abstract
digital domain to the real analog world. In many applications, DAC's play a
crucial role.
Due to variability in the production, various errors arise that influence the
performance of the DAC. We focus on the current errors, which describe the
fluctuations in the currents of the various unit current elements in the DAC. A
key performance measure of the DAC is the Integrated Non-linearity (INL), which
we study in this paper.
There are several DAC architectures. The most widely used architectures are
the thermometer, the binary and the segmented architectures. We study the two
extreme architectures, namely, the thermometer and the binary architectures. We
assume that the current errors are i.i.d. normally distributed, and reformulate
the INL as a functional of a Brownian bridge. We then proceed by investigating
these functionals. For the thermometer case, the functional is the maximal
absolute value of the Brownian bridge, which has been investigated in the
literature. For the binary case, we investigate properties of the functional,
such as its mean, variance and density.Comment: 22 pages, 4 figures. Version 2 with Section 3.6 added, and Section 4
revised. To appear in "Probability in the Engineering and Informational
Sciences
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