High accuracy computation with linear analog optical systems: a critical study

High accuracy optical processors based on the algorithm of digital multiplication by analog convolution (DMAC) are studied for ultimate performance limitations. Variations of optical processors that perform high accuracy vector-vector inner products are studied in abstract and with specific examples. It is concluded that the use of linear analog optical processors in performing digital computations with DMAC leads to impractical requirements for the accuracy of analog optical systems and the complexity of postprocessing electronics

Low-Jitter Clock Multiplication: a Comparioson between PLLs and DLLs

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts in the DLL. We can show that this effect is stronger than the notorious jitter accumulation effect that occurs in the voltage-controlled oscillator (VCO) of a PLL. First, an analysis of the stochastic-output jitter of the architectures, due to the most important noise sources, is presented. Then, another important source of jitter in a DLL-based clock multiplier is treated, namely the stochastic mismatch in the delay cells which compose the DLL voltage-controlled delay line (VCDL). An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. A circuit design technique, called impedance level scaling, is then presented which allows the designer to optimize the noise and mismatch behavior of a circuit, independently from other specifications such as speed and linearity. Applying this technique on a delay cell design yields a direct tradeoff between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage

Highly tunable repetition-rate multiplication of mode-locked lasers using all-fibre harmonic injection locking

Higher repetition-rate optical pulse trains have been desired for various applications such as high-bit-rate optical communication, photonic analogue-to-digital conversion, and multi- photon imaging. Generation of multi GHz and higher repetition-rate optical pulse trains directly from mode-locked oscillators is often challenging. As an alternative, harmonic injection locking can be applied for extra-cavity repetition-rate multiplication (RRM). Here we have investigated the operation conditions and achievable performances of all-fibre, highly tunable harmonic injection locking-based pulse RRM. We show that, with slight tuning of slave laser length, highly tunable RRM is possible from a multiplication factor of 2 to >100. The resulting maximum SMSR is 41 dB when multiplied by a factor of two. We further characterize the noise properties of the multiplied signal in terms of phase noise and relative intensity noise. The resulting absolute rms timing jitter of the multiplied signal is in the range of 20 fs to 60 fs (10 kHz - 1 MHz) for different multiplication factors. With its high tunability, simple and robust all-fibre implementation, and low excess noise, the demonstrated RRM system may find diverse applications in microwave photonics, optical communications, photonic analogue-to-digital conversion, and clock distribution networks.Comment: 25 pages, 9 figure

On the Implementation of Efficient Channel Filters for Wideband Receivers by Optimizing Common Subexpression Elimination Methods

No abstract availabl

Hardware/Software Co-design Applied to Reed-Solomon Decoding for the DMB Standard

This paper addresses the implementation of Reed- Solomon decoding for battery-powered wireless devices. The scope of this paper is constrained by the Digital Media Broadcasting (DMB). The most critical element of the Reed-Solomon algorithm is implemented on two different reconfigurable hardware architectures: an FPGA and a coarse-grained architecture: the Montium, The remaining parts are executed on an ARM processor. The results of this research show that a co-design of the ARM together with an FPGA or a Montium leads to a substantial decrease in energy consumption. The energy consumption of syndrome calculation of the Reed- Solomon decoding algorithm is estimated for an FPGA and a Montium by means of simulations. The Montium proves to be more efficient

Optimization of InP APDs for high-speed lightwave systems

Calculations based on a rigorous analytical model are carried out to optimize the width of the indium phosphide avalanche region in high-speed direct-detection avalanche photodiode-based optical receivers. The model includes the effects of intersymbol interference (ISI), tunneling current, avalanche noise, and its correlation with the stochastic avalanche duration, as well as dead space. A minimum receiver sensitivity of -28 dBm is predicted at an optimal width of 0.18 mu m and an optimal gain of approximately 13, for a 10 Gb/s communication system, assuming a Johnson noise level of 629 noise electrons per bit. The interplay among the factors controlling the optimum sensitivity is confirmed. Results show that for a given transmission speed, as the device width decreases below an optimum value, increased tunneling current outweighs avalanche noise reduction due to dead space, resulting in an increase in receiver sensitivity. As the device width increases above its optimum value, the receiver sensitivity increases as device bandwidth decreases, causing ISI to dominate avalanche noise and tunneling current shot noise