4 research outputs found

    Waveform narrowing : a constraint-based framework for timing analysis

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    Thèse numérisée par la Direction des bibliothèques de l'Université de Montréal

    A nonscan design-for-testability method for register-transfer-level circuits to guarantee linear-depth time expansion models

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    This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the tk notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclically testable class. Then, we introduce a new class of linear-depth time-bounded circuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called the cycle-unrollable RTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake et al Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing

    Voyager capsule, preliminary design, phase B. Volume III - Surface laboratory system. Section I - Surface laboratory Final report

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    Surface Laboratory preliminary configuration for Voyager mission - space capsul
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