10 research outputs found
Nonlinear time-domain macromodeling of OTA circuits
The authors present an accurate nonlinear macromodel of the operational transconductance amplifier (OTA) which is suitable for the transient simulation of OTA-based CMOS analog integrated circuits. As compared to device-level OTA models, the proposed macromodel is advantageous in terms of CPU time. Also, in circuits with many OTAs, it does not have the problems of convergence that the device-level MODEL has. All the macromodel parameters can be calculated from measurements made at the OTA terminals. Experimental results from a 3-ÎŒm CMOS OTA prototype as well as simulation results from device-level models are included and compared to simulation results from the macromodel
On the Design of Voltage-Controlled Sinusoidal Oscillators Using OTA's
A unified systematic approach to the design of voltage-controlled oscillators using only operational transconductance amplifiers (OTA's) and capacitors is discussed in this paper. Two classical oscillator models, i.e., quadrature and bandpass-based, are employed to generate several oscillator structures. They are very appropriate for silicon monolithic implementations. The resulting oscillation frequencies are proportional to the transconductance of the OTA and this makes the reported structures well-suited for building voltage controlled oscillators (VCO's). Amplitude stabilization circuits using both automatic gain control (AGC) mechanisms and limitation schemes are presented which are compatible with the transconductance amplifier capacitor oscillator (TACO). Experimental results from bipolar breadboard and CMOS IC prototypes are included showing good potential of OTA-based oscillators for high frequency VCO operation.ComisiĂłn Interministerial de Ciencia y TecnologĂa ME87-000
Nonlinearity and noise modeling of operational transconductance amplifiers for continuous time analog filters
A general framework for performance optimization of continuous-time OTA-C
(Operational Transconductance Amplifier-Capacitor) filters is proposed. Efficient
procedures for evaluating nonlinear distortion and noise valid for any filter of arbitrary
order are developed based on the matrix description of a general OTA-C filter model .
Since these procedures use OTA macromodels, they can be used to obtain the results
significantly faster than transistor-level simulation. In the case of transient analysis, the
speed-up may be as much as three orders of magnitude without almost no loss of
accuracy. This makes it possible to carry out direct numerical optimization of OTA-C
filters with respect to important characteristics such as noise performance, THD, IM3,
DR or SNR. On the other hand, the general OTA-C filter model allows us to apply
matrix transforms that manipulate (rescale) filter element values and/or change topology
without changing its transfer function. The above features are a basis to build automated
optimization procedures for OTA-C filters. In particular, a systematic optimization
procedure using equivalence transformations is proposed. The research also proposes
suitable software implementations of the optimization process. The first part of the
research proposes a general performance optimization procedure and to verify the
process two application type examples are mentioned. An application example of the
proposed approach to optimal block sequencing and gain distribution of 8th order
cascade Butterworth filter (for two variants of OTA topologies) is given. Secondly the
modeling tool is used to select the best suitable topology for a 5th order Bessel Low Pass
Filter. Theoretical results are verified by comparing to transistor-level simulation withCADENCE. For the purpose of verification, the filters have also been fabricated in
standard 0.5mm CMOS process.
The second part of the research proposes a new linearization technique to
improve the linearity of an OTA using an Active Error Feedforward technique. Most
present day applications require very high linear circuits combined with low noise and
low power consumption. An OTA based biquad filter has also been fabricated in 0.35mm
CMOS process. The measurement results for the filter and the stand alone OTA have
been discussed. The research focuses on these issues
Design considerations for integrated continuous-time chaotic oscillators
This paper presents an optimization procedure to choose the chaotic state equation which is best suited for implementation using Gm-C integrated circuit techniques. The paper also presents an analysis of the most significant hardware nonidealities of Gm-C circuits on the chaotic operation-the basis to design robust integrated circuits with reproducible and easily controllable behavior. The techniques in the paper are illustrated through a circuit fabricated in 2.4-/iin double-poly technology.ComisiĂłn Interministerial de Ciencia y TecnologĂa TIC 96-1392-CO2-
Can my chip behave like my brain?
Many decades ago, Carver Mead established the foundations of neuromorphic systems. Neuromorphic systems are analog circuits that emulate biology. These circuits utilize subthreshold dynamics of CMOS transistors to mimic the behavior of neurons. The objective is to not only simulate the human brain, but also to build useful applications using these bio-inspired circuits for ultra low power speech processing, image processing, and robotics. This can be achieved using reconfigurable hardware, like field programmable analog arrays (FPAAs), which enable configuring different applications on a cross platform system. As digital systems saturate in terms of power efficiency, this alternate approach has the potential to improve computational efficiency by approximately eight orders of magnitude. These systems, which include analog, digital, and neuromorphic elements combine to result in a very powerful reconfigurable processing machine.Ph.D
CMOS current amplifiers : speed versus nonlinearity
This work deals with analogue integrated circuit design using various types of current-mode amplifiers. These circuits are analysed and realised using modern CMOS integration technologies. The dynamic nonlinearities of these circuits are discussed in detail as in the literature only linear nonidealities and static nonlinearities are conventionally considered.
For the most important open-loop current-mode amplifier, the second-generation current-conveyor (CCII), a macromodel is derived that, unlike other reported macromodels, can accurately predict the common-mode behaviour in differential applications. Similarly, this model is used to describe the nonidealities of several other current-mode amplifiers because similar circuit structures are common in such amplifiers. With modern low-voltage CMOS-technologies, the current-mode operational amplifier and the high-gain current-conveyor (CCIIâ) perform better than open-loop current-amplifiers. Similarly, unlike with conventional voltage-mode operational amplifiers, the large-signal settling behaviour of these two amplifier types does not degrade as CMOS-processes are scaled down.
In this work, two 1 MHz 3rd -order low-pass continuous-time filters are realised with a 1.2 ÎŒm CMOS-process. These filters use a differential CCIIâ with linearised, dynamically biased output stages resulting in performance superior to most OTA-C filter realisations reported. Similarly, two logarithmic amplifier chips are designed and fabricated. The first circuit, implemented with a 1.2 ÎŒm BiCMOS-process, uses again a CCIIâ. This circuit uses a pn-junction as a logarithmic feedback element. With a CCIIâ the constant gain-bandwidth product, typical of voltage-mode operational amplifiers, is avoided resulting in a constant 1 MHz bandwidth with a 60 dB signal amplitude range. The second current-mode logarithmic amplifier, based on piece-wise linear approximation of the logarithmic function by a cascade of limiting current amplifier stages, is realised in a standard 1.2 ÎŒm CMOS-process. The limiting level in these current amplifiers is less sensitive to process variation than in limiting voltage amplifiers resulting in exceptionally low temperature dependency of the logarithmic output signal. Additionally, along with this logarithmic amplifier a new current peak detectoris developed.reviewe
On-Chip Analog Circuit Design Using Built-In Self-Test and an Integrated Multi-Dimensional Optimization Platform
Nowadays, the rapid development of system-on-chip (SoC) market introduces
tremendous complexity into the integrated circuit (IC) design. Meanwhile, the IC
fabrication process is scaling down to allow higher density of integration but makes
the chips more sensitive to the process-voltage-temperature (PVT) variations. A
successful IC product not only imposes great pressure on the IC designers, who have
to handle wider variations and enforce more design margins, but also challenges the
test procedure, leading to more check points and longer test time. To relax the
designersâ burden and reduce the cost of testing, it is valuable to make the IC chips
able to test and tune itself to some extent.
In this dissertation, a fully integrated in-situ design validation and optimization
(VO) hardware for analog circuits is proposed. It implements in-situ built-in self-test
(BIST) techniques for analog circuits. Based on the data collected from BIST,
the error between the measured and the desired performance of the target circuit is
evaluated using a cost function. A digital multi-dimensional optimization engine is
implemented to adaptively adjust the analog circuit parameters, seeking the minimum
value of the cost function and achieving the desired performance. To verify
this concept, study cases of a 2nd/4th active-RC band-pass filter (BPF) and a 2nd
order Gm-C BPF, as well as all BIST and optimization blocks, are adopted on-chip.
Apart from the VO system, several improved BIST techniques are also proposed
in this dissertation. A single-tone sinusoidal waveform generator based on a finite-impulse-response (FIR) architecture, which utilizes an optimization algorithm to
enhance its spur free dynamic range (SFDR), is proposed. It achieves an SFDR of
59 to 70 dBc from 150 to 850 MHz after the optimization procedure. A low-distortion
current-steering two-tone sinusoidal signal synthesizer based on a mixing-FIR architecture is also proposed. The two-tone synthesizer extends the FIR architecture to
two stages and implements an up-conversion mixer to generate the two tones, achieving better than -68 dBc IM3 below 480 MHz LO frequency without calibration.
Moreover, an on-chip RF receiver linearity BIST methodology for continuous and
discrete-time hybrid baseband chain is proposed. The proposed receiver chain
implements a charge-domain FIR filter to notch the two excitation signals but expose
the third order intermodulation (IM3) tones. It simplifies the linearity measurement
procedureâusing a power detector is enough to analyze the receiverâs linearity.
Finally, a low cost fully digital built-in analog tester for linear-time-invariant
(LTI) analog blocks is proposed. It adopts a time-to-digital converter (TDC) to
measure the delays corresponded to a ramp excitation signal and is able to estimate
the pole or zero locations of a low-pass LTI system