Single-amplifier integrator-based low power CMOS filter for video frequency applications

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”This paper describes a new low power fully differential second-order continuous-time low pass filter for use at video frequencies. The filter uses a single active device in combination with MOSFET resistors and grounded capacitors to achieve very low power consumption, small chip area and large dynamic range. The ideal integrator is realised using an internally compensated opamp consisting of only current mirrors and voltage buffers, whilst the lossy integrator is implemented by a single passive RC circuit. The filter has been simulated using a CMOS process. Results show that with a single 5 V power supply, cut-off frequency can be tuned from 3.5 MHz to 8 MHz, dynamic range is better than 67 dB, and power consumption is less than 1.7 mW

A 0.18µm CMOS DDCCII for Portable LV-LP Filters

In this paper a current mode very low voltage (LV) (1V) and low power (LP) (21 µW) differential difference second generation current conveyor (CCII) is presented. The circuit is developed by applying the current sensing technique to a fully balanced version of a differential difference amplifier (DDA) so to design a suitable LV LP integrated version of the so-called differential difference CCII (DDCCII). Post-layout results, using a 0.18µm SMIC CMOS technology, have shown good general circuit performances making the proposed circuit suitable for fully integration in battery portable systems as, for examples, fully differential Sallen-Key bandpass filter

Particle-filtering approaches for nonlinear Bayesian decoding of neuronal spike trains

The number of neurons that can be simultaneously recorded doubles every seven years. This ever increasing number of recorded neurons opens up the possibility to address new questions and extract higher dimensional stimuli from the recordings. Modeling neural spike trains as point processes, this task of extracting dynamical signals from spike trains is commonly set in the context of nonlinear filtering theory. Particle filter methods relying on importance weights are generic algorithms that solve the filtering task numerically, but exhibit a serious drawback when the problem dimensionality is high: they are known to suffer from the 'curse of dimensionality' (COD), i.e. the number of particles required for a certain performance scales exponentially with the observable dimensions. Here, we first briefly review the theory on filtering with point process observations in continuous time. Based on this theory, we investigate both analytically and numerically the reason for the COD of weighted particle filtering approaches: Similarly to particle filtering with continuous-time observations, the COD with point-process observations is due to the decay of effective number of particles, an effect that is stronger when the number of observable dimensions increases. Given the success of unweighted particle filtering approaches in overcoming the COD for continuous- time observations, we introduce an unweighted particle filter for point-process observations, the spike-based Neural Particle Filter (sNPF), and show that it exhibits a similar favorable scaling as the number of dimensions grows. Further, we derive rules for the parameters of the sNPF from a maximum likelihood approach learning. We finally employ a simple decoding task to illustrate the capabilities of the sNPF and to highlight one possible future application of our inference and learning algorithm

Passivity-based harmonic control through series/parallel damping of an H-bridge rectifier

Nowadays the H-bridge is one of the preferred solutions to connect DC loads or distributed sources to the single-phase grid. The control aims are: sinusoidal grid current with unity power factor and optimal DC voltage regulation capability. These objectives should be satisfied, regardless the conditions of the grid, the DC load/source and the converter nonlinearities. In this paper a passivity-based approach is thoroughly investigated proposing a damping-based solution for the error dynamics. Practical experiments with a real converter validate the analysis.

Design of a silicon cochlea system with biologically faithful response

This paper presents the design and simulation results of a silicon cochlea system that has closely similar behavior as the real cochlea. A cochlea filter-bank based on the improved three-stage filter cascade structure is used to model the frequency decomposition function of the basilar membrane; a filter tuning block is designed to model the adaptive response of the cochlea; besides, an asynchronous event-triggered spike codec is employed as the system interface with bank-end spiking neural networks. As shown in the simulation results, the system has biologically faithful frequency response, impulse response, and active adaptation behavior; also the system outputs multiple band-pass channels of spikes from which the original sound input can be recovered. The proposed silicon cochlea is feasible for analog VLSI implementation so that it not only emulates the way that sounds are preprocessed in human ears but also is able match the compact physical size of a real cochlea