Carrier Transport in High Mobility InAs Nanowire Junctionless Transistors

Ability to understand and model the performance limits of nanowire transistors is the key to design of next generation devices. Here, we report studies on high-mobility junction-less gate-all-around nanowire field effect transistor with carrier mobility reaching 2000 cm2/V.s at room temperature. Temperature-dependent transport measurements reveal activated transport at low temperatures due to surface donors, while at room temperature the transport shows a diffusive behavior. From the conductivity data, the extracted value of sound velocity in InAs nanowires is found to be an order less than the bulk. This low sound velocity is attributed to the extended crystal defects that ubiquitously appear in these nanowires. Analyzing the temperature-dependent mobility data, we identify the key scattering mechanisms limiting the carrier transport in these nanowires. Finally, using these scattering models, we perform drift-diffusion based transport simulations of a nanowire field-effect transistor and compare the device performances with experimental measurements. Our device modeling provides insight into performance limits of InAs nanowire transistors and can be used as a predictive methodology for nanowire-based integrated circuits.Comment: 22 pages, 5 Figures, Nano Letter

DC performance analysis of a 20nm gate lenght n-type silicon GAA junctionless (Si JL-GAA) transistor

With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model .This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity . The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversion-mode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion / Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV / V

Realizing lateral wrap-gated nanowire FETs: Controlling gate length with chemistry rather than lithography

An important consideration in miniaturizing transistors is maximizing the coupling between the gate and the semiconductor channel. A nanowire with a coaxial metal gate provides optimal gate-channel coupling, but has only been realized for vertically oriented nanowire transistors. We report a method for producing laterally oriented wrap-gated nanowire field-effect transistors that provides exquisite control over the gate length via a single wet etch step, eliminating the need for additional lithography beyond that required to define the source/drain contacts and gate lead. It allows the contacts and nanowire segments extending beyond the wrap-gate to be controlled independently by biasing the doped substrate, significantly improving the sub-threshold electrical characteristics. Our devices provide stronger, more symmetric gating of the nanowire, operate at temperatures between 300 to 4 Kelvin, and offer new opportunities in applications ranging from studies of one-dimensional quantum transport through to chemical and biological sensing.Comment: 16 pages, 5 figures. Submitted version, published version available at http://http://pubs.acs.org/journal/nalef

A sectorial scheme of gate-all-around field effect transistor with improved electrical characteristics

Reliability and controllability for a new scheme of gate-all-around field effect transistor (GAA-FET) with a silicon channel utilizing a sectorial cross section is evaluated in terms of Ion/Ioff current ratio, transconductance, subthreshold slope, threshold voltage roll-off, and drain induced barrier lowering (DIBL). In addition, the scaling behavior of electronic figures of merit is comprehensively studied with the aid of physical simulations. The electrical characteristic of proposed structure is compared with a circular GAA-FET, which is previously calibrated with an IBM sample at the 22 nm channel length using 3D-TCAD simulations. Our simulation results show that sectorial cross section GAA-FET is a superior structure for controlling short channel effects (SCEs) and to obtain better performance compared to conventional circular cross section counterpart

Nasics: A `Fabric-Centric\u27 Approach Towards Integrated Nanosystems

This dissertation addresses the fundamental problem of how to build computing systems for the nanoscale. With CMOS reaching fundamental limits, emerging nanomaterials such as semiconductor nanowires, carbon nanotubes, graphene etc. have been proposed as promising alternatives. However, nanoelectronics research has largely focused on a `device-first\u27 mindset without adequately addressing system-level capabilities, challenges for integration and scalable assembly. In this dissertation, we propose to develop an integrated nano-fabric, (broadly defined as nanostructures/devices in conjunction with paradigms for assembly, inter-connection and circuit styles), as opposed to approaches that focus on MOSFET replacement devices as the ultimate goal. In the `fabric-centric\u27 mindset, design choices at individual levels are made compatible with the fabric as a whole and minimize challenges for nanomanufacturing while achieving system-level benefits vs. scaled CMOS. We present semiconductor nanowire based nano-fabrics incorporating these fabric-centric principles called NASICs and N3ASICs and discuss how we have taken them from initial design to experimental prototype. Manufacturing challenges are mitigated through careful design choices at multiple levels of abstraction. Regular fabrics with limited customization mitigate overlay alignment requirements. Cross-nanowire FET devices and interconnect are assembled together as part of the uniform regular fabric without the need for arbitrary fine-grain interconnection at the nanoscale, routing or device sizing. Unconventional circuit styles are devised that are compatible with regular fabric layouts and eliminate the requirement for using complementary devices. Core fabric concepts are introduced and validated. Detailed analyses on device-circuit co-design and optimization, cascading, noise and parameter variation are presented. Benchmarking of nanowire processor designs vs. equivalent scaled 16nm CMOS shows up to 22X area, 30X power benefits at comparable performance, and with overlay precision that is achievable with present-day technology. Building on the extensive manufacturing-friendly fabric framework, we present recent experimental efforts and key milestones that have been attained towards realizing a proof-of-concept prototype at dimensions of 30nm and below

Gallium Nitride Nanowire Based Electronic and Optical Devices

Gallium nitride nanowires have significant potential for developing nanoscale emitters, detectors, and biological/chemical sensors, as they possess unique material properties such as wide direct bandgap (3.4 eV), high critical breakdown field, radiation hardness, and mechanical/chemical stability. Although few results of individual GaN nanowire devices have been reported so far, most of them often utilize fabrication processes unsuitable for large-scale nanosystems development and do not involve fundamental transport property measurements. Understanding the transport mechanisms and correlating the device properties with the structural characteristics of the nanowires are of great importance for realizing high performance devices. Focused ion beam induced metal deposition was used to make individual GaN nanowire devices, and assessment of their electrical properties was performed. The nanowires were grown by direct reaction of Ga and NH3, with diameters ranging from 80 nm to 250 nm and lengths up to 200 µm. Dielectrophoretic alignment was used to assemble these nanowires from a suspension on to a large area pre-patterned substrate. A fabrication technique, utilizing only conventional microfabrication processes, has been developed for realizing robust nanowire devices including field effect transistors (FETs), light emitting diodes (LEDs), Schottky diodes, and four-terminal structures. Nanowire FETs with different gate geometries were studied, namely bottom gate, omega-backgate, and omega-plane gate structures. Utilizing omega-backgated FETs, transconductance as high as 0.34 103 µS mm-1 has been obtained. Room temperature field effect electron mobility in excess of 300 cm2 V-1 s-1 have been exhibited by a nanowire FET, with a 200 nm diameter nanowire and Si substrate as the backgate. The observed reduction of mobility in the GaN nanowire FETs with decreasing diameter of the nanowire is attributed to the surface scattering. Electron beam backscattered diffraction revealed that the grain boundary scattering is present in some of the nanowires. Temperature dependent mobility measurements indicated that the ionized impurity scattering is the dominant mechanism in the transport in these nanowires. GaN nanoLEDs have been realized by assembling the n-type nanowires on a p-GaN epitaxial layer using dielectrophoresis. The resulting p-n homojunctions exhibited 365 nm electroluminescence with a full width half maximum of 25 nm at 300 K

Impact of high-k gate dielectric with different angles of coverage on the electrical characteristics of gate-all-around field effect transistor: a simulation study

In this paper, we consider the electrical performance of a circular cross section gate all around-field effect transistor (GAA-FET) in which gate dielectric coverage with high-k dielectric (HfO2) over the channel region has been varied. Our simulations show the fact that as high-k dielectric coverage over the channel increases, ION/IOFF ratio and transconductance over drain current (gm/ID) will be enhanced. Moreover, we investigate the impact of channel length scaling on these devices. The obtained results show that subthreshold slope (SS), drain induced barrier lowering (DIBL) and threshold voltage (VTH) roll-off will be reduced as a result of scaling. In this work TCAD simulator was concisely calibrated against experimental data of a GAA-FET from IBM. The Schrödinger equation is solved in the transverse direction and quantum mechanical confinement effects are taken into account

Impact of multiple channels on the Characteristics of Rectangular GAA MOSFET

Square gate all around MOSFETs are a very promising device structures allowing to continue scaling due to their superior control over the short channel effects. In this work a numerical study of a square structure with single channel is compared to a structure with 4 channels in order to highlight the impact of channels number on the device’s DC parameters (drain current and threshold voltage). Our single channel rectangular GAA MOSFET showed reasonable ratio Ion/Ioff of 104, while our four channels GAA MOSFET showed a value of 103. In addition, a low value of drain induced barrier lowering (DIBL) of 60mV/V was obtained for our single channel GAA and a lower value of with 40mv/v has been obtained for our four channel one. Also, an extrinsic transconductance of 88ms/µm have been obtained for our four channels GAA compared to the single channel that is equal to 7ms/µm

Arithmetic logic unit design for silicon nanowire field-effect transistors logic

As dimensions of conventional planar metal-oxide-semiconductor field effect transistor (MOSFET) are reduced, it cause a lot challenging issue such as short-channel effects (SCEs), scaling of gate oxide thickness and increase power consumption. Multigate such as double gate, tri-gate, surrounding gate and FinFET has been studied as potential structure to replace MOSFET. Thus this research report will describes the simulation and characterization of surrounded gate Silicon Nanowires Transistor (Si NWT). The cylindrical Gate-all around (GAA) Si NWT has showed robustness against SCE, ideal sub threshold swing, suppresses corner effect and suitable for low power devices. From this study simulation had proven that GAA Si NWT provides the best short channel device performance. Also highlighted in this research studies, to achieve symmetrical current in PMOS and NMOS, different number of nanowires channel is selected. Therefore by choosing large number of nanowires channel for PMOS transistor can help compensated the low value of hole mobility. In this work, 2:3 ratios of NMOS and PMOS channel of inverter had used as benchmark for ALU designed. Using the circuit modeling HSPICE, performance for Arithmetic Logic Unit (ALU) circuit in 30nm technology is analyzed with Silicon Nanowire (Si NW) compared with conventional planar MOSFET. The assessment of this circuit logic performance metric includes propagation delay, power-delay-product (PDP) and energy-delay-product (EDP) of full adder, XOR, AND and OR gate forming the ALU block. Moreover, ALU is built with less transistor count to implement Boolean expressions which help to reduced average power consumption, and delay