Remote experimental station for engineering education

This thesis provides a distance-learning laboratory for students of electrical and computer engineering department where the instructor can conduct experiments on a computer and send the results to the students at remote computers. The output of the experiment conducted by the instructor is sampled using a successive approximation Analog to Digital (A/D) converter. A microcontroller collects samples using high speed queued serial peripheral interface clock and transmits data to IBM-compatible personal computer over a serial port interface, where the samples are processed using Fast Fourier Transforms and graphed. The client/server application developed transfers the acquired samples over Transmission Control Protocol/Internet Protocol (TCP/IP) network with operational Graphical User Interface (GUI) to the remote computers where the samples are processed and presented to students. The application was tested on all Windows platforms and various Internet speeds (56k modem, Digital Subscriber Line (DSL), Local Area Network (LAN)). The results were analyzed and appropriate methodology of Remote Experimental Station was formulated

Conception pour la testabilité des systèmes biomédicaux implantables

Architecture générale des systèmes implantables -- Principes de stimulation électrique -- Champs d'application des systèmes implantables -- Les particularités des circuits implantables -- Tendance future -- Conception pour la testabilité de la partie numérique des circuits implantables -- "Desigh and realization of an accurate built-in current sensor for Iddq testing and power dissipation measurement -- Conception pour la testabilité de la partie analogique des circuits implantables -- BIST for digital-to-analog and Analogo-to-digital converters -- Efficient and accurate testing of analog-to-digital converters using oscillation test method -- Design for testability of Embedded integrated operational amplifiers -- Vérification des interfaces bioélectroniques des systèmes implantables -- Monitorin the electrode and lead failures in implanted microstimulators and sensors -- Capteurs de température intégrés pour la vérification de l'état thermique des puces dédiées -- Built-in temperature sensors for on-line thermal monitoring of microelectronic structures -- Un protocole de communication fiable pour la programmation et la télémétrie des système implantables -- A reliable communication protoco for externally controlled biomedical implanted devices

Development of a 6-bit 15.625 MHz CMOS two-step flash analog-to-digital converter for a low dead time sub-nanosecond time measurement system

The development of a 6-bit 15.625 MHz CMOS two-step analog-to-digital converter (ADC) is presented. The ADC was developed for use in a low dead time, high-performance, sub-nanosecond time-to-digital converter (TDC). The TDC is part of a new custom CMOS application specific integrated circuit (ASIC) that will be incorporated in the next generation of front-end electronics for high-performance positron emission tomography imaging. The ADC is based upon a two-step flash architecture that reduces the comparator count by a factor-of-two when compared to a traditional flash ADC architecture and thus a significant reduction in area, power dissipation, and input capacitance of the converter is achieved. The converter contains time-interleaved auto-zeroed CMOS comparators. These comparators utilize offset correction in both the preamplifier and the subsequent regenerative latch stage to guarantee good integral and differential non-linearity performance of the converter over extreme process conditions. Also, digital error correction was employed to overcome most of the major metastability problems inherent in flash converters and to guarantee a completely monotonic transfer function. Corrected comparator offset measurements reveal that the CMOS comparator design maintains a worse case input-referred offset of less than 1 mV at conversion rates up to 8 MHz and less than a 2 mV offset at conversion rates as high as 16 MHz while dissipating less than 2.6 mW. Extensive laboratory measurements indicate that the ADC achieves differential and integral non-linearity performance of less than ±1/2 LSB with a 20 mV/LSB resolution. The ADC dissipates 90 mW from a single 5 V supply and occupies a die area of 1.97 mm x 1.13 mm in 0.8 μm CMOS technology

Energy-efficient analog-to-digital conversion for ultra-wideband radio

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 207-222).In energy constrained signal processing and communication systems, a focus on the analog or digital circuits in isolation cannot achieve the minimum power consumption. Furthermore, in advanced technologies with significant variation, yield is traditionally achieved only through conservative design and a sacrifice of energy efficiency. In this thesis, these limitations are addressed with both a comprehensive mixed-signal design methodology and new circuits and architectures, as presented in the context of an analog-to-digital converter (ADC) for ultra-wideband (UWB) radio. UWB is an emerging technology capable of high-data-rate wireless communication and precise locationing, and it requires high-speed (>500MS/s), low-resolution ADCs. The successive approximation register (SAR) topology exhibits significantly reduced complexity compared to the traditional flash architecture. Three time-interleaved SAR ADCs have been implemented. At the mixed-signal optimum energy point, parallelism and reduced voltage supplies provide more than 3x energy savings. Custom control logic, a new capacitive DAC, and a hierarchical sampling network enable the high-speed operation. Finally, only a small amount of redundancy, with negligible power penalty, dramatically improves the yield of the highly parallel ADC in deep sub-micron CMOS.by Brian P. Ginsburg.Ph.D

Design techniques for low-voltage analog-to-digital converter

Continuous process scale-down and emerging markets for low-power/low-voltage mobile systems call for low-voltage analog integrated circuits. Switched-capacitor circuits are the building blocks for analog signal processing and will encounter severe overdrive problems when operating at low-voltage conditions. There are several well-known techniques to bypass the problem. These approaches include: (1) The clock boosting schemes (e.g. 2VDD clock signal) which cannot be used in submicron low-voltage CMOS processes as gate oxide can only tolerate the technology's maximum voltage (VDD). (2) The use of scaled/lower threshold transistors, which are not always scalable to very low voltage supplies as it could suffer from an unacceptable amount of leakage current (e.g. the switch may not be fully turned off). (3) The use of bootstrapped clocking, which has added loading and possible reliability issues. (4) The switched-opamp (SO) technique which is fully compatible with low-voltage submicron CMOS processes but the operating speed limited due to slow transients from the opamp being switched off and on. In this thesis, the Opamp-Reset Switching Technique (ORST) topology is proposed for low-voltage operation. Instead of opamps being turned on and off as in the switched-opamp technique, the sourcing amplifier is placed in the unity-gain reset configuration to provide reset level at the output. In this way, high-speed operation is possible. The technique is applied to two ADCs as examples of low-voltage design. The first design is a 10-bit 25MSPS pipelined ADC using pseudo-differential structure. It is fabricated in a 0.35-μm CMOS process. It operates at 1.4V and consumes 21mW of total power. The second design is a two-stage algorithmic ADC with highly linear input sampling circuit. In addition to the low-voltage design techniques used in the pipelined ADC, radix-based digital calibration technique for multi-stage ADC is also proposed. The ADC uses a 0.18-μm CMOS technology. It operates at 0.9V supply with total power consumption of 9mW. Experimental results show that the proposed calibration technique reduces spurious free dynamic range from 47dB to 75dB and improves signal-to-noise and distortion ratio from 40dB to 55dB after calibration